Mercurial > hg > Members > tobaru > cbc > CbC_llvm
comparison test/CodeGen/ARM/fold-stack-adjust.ll @ 95:afa8332a0e37
LLVM 3.8
author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
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date | Tue, 13 Oct 2015 17:48:58 +0900 |
parents | 60c9769439b8 |
children | 7d135dc70f03 |
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84:f3e34b893a5f | 95:afa8332a0e37 |
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10 | 10 |
11 @var = global %bigVec zeroinitializer | 11 @var = global %bigVec zeroinitializer |
12 | 12 |
13 define void @check_simple() minsize { | 13 define void @check_simple() minsize { |
14 ; CHECK-LABEL: check_simple: | 14 ; CHECK-LABEL: check_simple: |
15 ; CHECK: push.w {r7, r8, r9, r10, r11, lr} | 15 ; CHECK: push {r3, r4, r5, r6, r7, lr} |
16 ; CHECK-NOT: sub sp, sp, | 16 ; CHECK-NOT: sub sp, sp, |
17 ; ... | 17 ; ... |
18 ; CHECK-NOT: add sp, sp, | 18 ; CHECK-NOT: add sp, sp, |
19 ; CHECK: pop.w {r0, r1, r2, r3, r11, pc} | 19 ; CHECK: pop {r0, r1, r2, r3, r7, pc} |
20 | 20 |
21 ; CHECK-T1-LABEL: check_simple: | 21 ; CHECK-T1-LABEL: check_simple: |
22 ; CHECK-T1: push {r3, r4, r5, r6, r7, lr} | 22 ; CHECK-T1: push {r3, r4, r5, r6, r7, lr} |
23 ; CHECK-T1: add r7, sp, #16 | 23 ; CHECK-T1: add r7, sp, #16 |
24 ; CHECK-T1-NOT: sub sp, sp, | 24 ; CHECK-T1-NOT: sub sp, sp, |
42 ret void | 42 ret void |
43 } | 43 } |
44 | 44 |
45 define void @check_simple_too_big() minsize { | 45 define void @check_simple_too_big() minsize { |
46 ; CHECK-LABEL: check_simple_too_big: | 46 ; CHECK-LABEL: check_simple_too_big: |
47 ; CHECK: push.w {r11, lr} | 47 ; CHECK: push {r7, lr} |
48 ; CHECK: sub sp, | 48 ; CHECK: sub sp, |
49 ; ... | 49 ; ... |
50 ; CHECK: add sp, | 50 ; CHECK: add sp, |
51 ; CHECK: pop.w {r11, pc} | 51 ; CHECK: pop {r7, pc} |
52 %var = alloca i8, i32 64 | 52 %var = alloca i8, i32 64 |
53 call void @bar(i8* %var) | 53 call void @bar(i8* %var) |
54 ret void | 54 ret void |
55 } | 55 } |
56 | 56 |
58 ; CHECK-LABEL: check_vfp_fold: | 58 ; CHECK-LABEL: check_vfp_fold: |
59 ; CHECK: push {r[[GLOBREG:[0-9]+]], lr} | 59 ; CHECK: push {r[[GLOBREG:[0-9]+]], lr} |
60 ; CHECK: vpush {d6, d7, d8, d9} | 60 ; CHECK: vpush {d6, d7, d8, d9} |
61 ; CHECK-NOT: sub sp, | 61 ; CHECK-NOT: sub sp, |
62 ; ... | 62 ; ... |
63 ; CHECK: vldmia r[[GLOBREG]], {d8, d9} | |
64 ; ... | |
65 ; CHECK-NOT: add sp, | 63 ; CHECK-NOT: add sp, |
66 ; CHECK: vpop {d6, d7, d8, d9} | 64 ; CHECK: vpop {d6, d7, d8, d9} |
67 ; CHECKL pop {r[[GLOBREG]], pc} | 65 ; CHECK: pop {r[[GLOBREG]], pc} |
68 | 66 |
69 ; iOS uses aligned NEON stores here, which is convenient since we | 67 ; iOS uses aligned NEON stores here, which is convenient since we |
70 ; want to make sure that works too. | 68 ; want to make sure that works too. |
71 ; CHECK-IOS-LABEL: check_vfp_fold: | 69 ; CHECK-IOS-LABEL: check_vfp_fold: |
72 ; CHECK-IOS: push {r0, r1, r2, r3, r4, r7, lr} | 70 ; CHECK-IOS: push {r4, r7, lr} |
73 ; CHECK-IOS: sub.w r4, sp, #16 | 71 ; CHECK-IOS: sub.w r4, sp, #16 |
74 ; CHECK-IOS: bfc r4, #0, #4 | 72 ; CHECK-IOS: bfc r4, #0, #4 |
75 ; CHECK-IOS: mov sp, r4 | 73 ; CHECK-IOS: mov sp, r4 |
76 ; CHECK-IOS: vst1.64 {d8, d9}, [r4:128] | 74 ; CHECK-IOS: vst1.64 {d8, d9}, [r4:128] |
75 ; CHECK-IOS: sub sp, #16 | |
77 ; ... | 76 ; ... |
78 ; CHECK-IOS: add r4, sp, #16 | 77 ; CHECK-IOS: add r4, sp, #16 |
79 ; CHECK-IOS: vld1.64 {d8, d9}, [r4:128] | 78 ; CHECK-IOS: vld1.64 {d8, d9}, [r4:128] |
80 ; CHECK-IOS: mov sp, r4 | 79 ; CHECK-IOS: mov sp, r4 |
81 ; CHECK-IOS: pop {r4, r7, pc} | 80 ; CHECK-IOS: pop {r4, r7, pc} |
82 | 81 |
83 %var = alloca i8, i32 16 | 82 %var = alloca i8, i32 16 |
84 | 83 |
85 %tmp = load %bigVec* @var | 84 call void asm "", "r,~{d8},~{d9}"(i8* %var) |
86 call void @bar(i8* %var) | 85 call void @bar(i8* %var) |
87 store %bigVec %tmp, %bigVec* @var | |
88 | 86 |
89 ret void | 87 ret void |
90 } | 88 } |
91 | 89 |
92 ; This function should use just enough space that the "add sp, sp, ..." could be | 90 ; This function should use just enough space that the "add sp, sp, ..." could be |
93 ; folded in except that doing so would clobber the value being returned. | 91 ; folded in except that doing so would clobber the value being returned. |
94 define i64 @check_no_return_clobber() minsize { | 92 define i64 @check_no_return_clobber() minsize { |
95 ; CHECK-LABEL: check_no_return_clobber: | 93 ; CHECK-LABEL: check_no_return_clobber: |
96 ; CHECK: push.w {r5, r6, r7, r8, r9, r10, r11, lr} | 94 ; CHECK: push {r1, r2, r3, r4, r5, r6, r7, lr} |
97 ; CHECK-NOT: sub sp, | 95 ; CHECK-NOT: sub sp, |
98 ; ... | 96 ; ... |
99 ; CHECK: add sp, #24 | 97 ; CHECK: add sp, #24 |
100 ; CHECK: pop.w {r11, pc} | 98 ; CHECK: pop {r7, pc} |
101 | 99 |
102 ; Just to keep iOS FileCheck within previous function: | 100 ; Just to keep iOS FileCheck within previous function: |
103 ; CHECK-IOS-LABEL: check_no_return_clobber: | 101 ; CHECK-IOS-LABEL: check_no_return_clobber: |
104 | 102 |
105 %var = alloca i8, i32 20 | 103 %var = alloca i8, i32 20 |
117 ; CHECK: vpop {d8, d9} | 115 ; CHECK: vpop {d8, d9} |
118 ; CHECK: pop {r[[GLOBREG]], pc} | 116 ; CHECK: pop {r[[GLOBREG]], pc} |
119 | 117 |
120 %var = alloca i8, i32 64 | 118 %var = alloca i8, i32 64 |
121 | 119 |
122 %tmp = load %bigVec* @var | 120 %tmp = load %bigVec, %bigVec* @var |
123 call void @bar(i8* %var) | 121 call void @bar(i8* %var) |
124 store %bigVec %tmp, %bigVec* @var | 122 store %bigVec %tmp, %bigVec* @var |
125 | 123 |
126 ret double 1.0 | 124 ret double 1.0 |
127 } | 125 } |
150 ; We want some memory so there's a stack adjustment to fold... | 148 ; We want some memory so there's a stack adjustment to fold... |
151 %var = alloca i8, i32 8 | 149 %var = alloca i8, i32 8 |
152 | 150 |
153 ; We want a long-lived floating register so that a callee-saved dN is used and | 151 ; We want a long-lived floating register so that a callee-saved dN is used and |
154 ; there's both a vpop and a pop. | 152 ; there's both a vpop and a pop. |
155 %live_val = load double* @dbl | 153 %live_val = load double, double* @dbl |
156 br i1 %tst, label %true, label %end | 154 br i1 %tst, label %true, label %end |
157 true: | 155 true: |
158 call void @bar(i8* %var) | 156 call void @bar(i8* %var) |
159 store double %live_val, double* @dbl | 157 store double %live_val, double* @dbl |
160 br label %end | 158 br label %end |
168 ; CHECK-T1-LABEL: test_varsize: | 166 ; CHECK-T1-LABEL: test_varsize: |
169 ; CHECK-T1: sub sp, #16 | 167 ; CHECK-T1: sub sp, #16 |
170 ; CHECK-T1: push {r5, r6, r7, lr} | 168 ; CHECK-T1: push {r5, r6, r7, lr} |
171 ; ... | 169 ; ... |
172 ; CHECK-T1: pop {r2, r3, r7} | 170 ; CHECK-T1: pop {r2, r3, r7} |
173 ; CHECK-T1: pop {r3} | 171 ; CHECK-T1: pop {[[POP_REG:r[0-3]]]} |
174 ; CHECK-T1: add sp, #16 | 172 ; CHECK-T1: add sp, #16 |
175 ; CHECK-T1: bx r3 | 173 ; CHECK-T1: bx [[POP_REG]] |
176 | 174 |
177 ; CHECK-LABEL: test_varsize: | 175 ; CHECK-LABEL: test_varsize: |
178 ; CHECK: sub sp, #16 | 176 ; CHECK: sub sp, #16 |
179 ; CHECK: push.w {r9, r10, r11, lr} | 177 ; CHECK: push {r5, r6, r7, lr} |
180 ; ... | 178 ; ... |
181 ; CHECK: pop.w {r2, r3, r11, lr} | 179 ; CHECK: pop.w {r2, r3, r7, lr} |
182 ; CHECK: add sp, #16 | 180 ; CHECK: add sp, #16 |
183 ; CHECK: bx lr | 181 ; CHECK: bx lr |
184 | 182 |
185 %var = alloca i8, i32 8 | 183 %var = alloca i8, i32 8 |
186 call void @llvm.va_start(i8* %var) | 184 call void @llvm.va_start(i8* %var) |