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comparison test/CodeGen/ARM/vrev.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children
comparison
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84:f3e34b893a5f 95:afa8332a0e37
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
2 2
3 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { 3 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
4 ;CHECK-LABEL: test_vrev64D8: 4 ;CHECK-LABEL: test_vrev64D8:
5 ;CHECK: vrev64.8 5 ;CHECK: vrev64.8
6 %tmp1 = load <8 x i8>* %A 6 %tmp1 = load <8 x i8>, <8 x i8>* %A
7 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> 7 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
8 ret <8 x i8> %tmp2 8 ret <8 x i8> %tmp2
9 } 9 }
10 10
11 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { 11 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
12 ;CHECK-LABEL: test_vrev64D16: 12 ;CHECK-LABEL: test_vrev64D16:
13 ;CHECK: vrev64.16 13 ;CHECK: vrev64.16
14 %tmp1 = load <4 x i16>* %A 14 %tmp1 = load <4 x i16>, <4 x i16>* %A
15 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> 15 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
16 ret <4 x i16> %tmp2 16 ret <4 x i16> %tmp2
17 } 17 }
18 18
19 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { 19 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
20 ;CHECK-LABEL: test_vrev64D32: 20 ;CHECK-LABEL: test_vrev64D32:
21 ;CHECK: vrev64.32 21 ;CHECK: vrev64.32
22 %tmp1 = load <2 x i32>* %A 22 %tmp1 = load <2 x i32>, <2 x i32>* %A
23 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0> 23 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
24 ret <2 x i32> %tmp2 24 ret <2 x i32> %tmp2
25 } 25 }
26 26
27 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { 27 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
28 ;CHECK-LABEL: test_vrev64Df: 28 ;CHECK-LABEL: test_vrev64Df:
29 ;CHECK: vrev64.32 29 ;CHECK: vrev64.32
30 %tmp1 = load <2 x float>* %A 30 %tmp1 = load <2 x float>, <2 x float>* %A
31 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0> 31 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
32 ret <2 x float> %tmp2 32 ret <2 x float> %tmp2
33 } 33 }
34 34
35 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { 35 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
36 ;CHECK-LABEL: test_vrev64Q8: 36 ;CHECK-LABEL: test_vrev64Q8:
37 ;CHECK: vrev64.8 37 ;CHECK: vrev64.8
38 %tmp1 = load <16 x i8>* %A 38 %tmp1 = load <16 x i8>, <16 x i8>* %A
39 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> 39 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
40 ret <16 x i8> %tmp2 40 ret <16 x i8> %tmp2
41 } 41 }
42 42
43 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { 43 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
44 ;CHECK-LABEL: test_vrev64Q16: 44 ;CHECK-LABEL: test_vrev64Q16:
45 ;CHECK: vrev64.16 45 ;CHECK: vrev64.16
46 %tmp1 = load <8 x i16>* %A 46 %tmp1 = load <8 x i16>, <8 x i16>* %A
47 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> 47 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
48 ret <8 x i16> %tmp2 48 ret <8 x i16> %tmp2
49 } 49 }
50 50
51 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { 51 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
52 ;CHECK-LABEL: test_vrev64Q32: 52 ;CHECK-LABEL: test_vrev64Q32:
53 ;CHECK: vrev64.32 53 ;CHECK: vrev64.32
54 %tmp1 = load <4 x i32>* %A 54 %tmp1 = load <4 x i32>, <4 x i32>* %A
55 %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 55 %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
56 ret <4 x i32> %tmp2 56 ret <4 x i32> %tmp2
57 } 57 }
58 58
59 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { 59 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
60 ;CHECK-LABEL: test_vrev64Qf: 60 ;CHECK-LABEL: test_vrev64Qf:
61 ;CHECK: vrev64.32 61 ;CHECK: vrev64.32
62 %tmp1 = load <4 x float>* %A 62 %tmp1 = load <4 x float>, <4 x float>* %A
63 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 63 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
64 ret <4 x float> %tmp2 64 ret <4 x float> %tmp2
65 } 65 }
66 66
67 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { 67 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
68 ;CHECK-LABEL: test_vrev32D8: 68 ;CHECK-LABEL: test_vrev32D8:
69 ;CHECK: vrev32.8 69 ;CHECK: vrev32.8
70 %tmp1 = load <8 x i8>* %A 70 %tmp1 = load <8 x i8>, <8 x i8>* %A
71 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> 71 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
72 ret <8 x i8> %tmp2 72 ret <8 x i8> %tmp2
73 } 73 }
74 74
75 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { 75 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
76 ;CHECK-LABEL: test_vrev32D16: 76 ;CHECK-LABEL: test_vrev32D16:
77 ;CHECK: vrev32.16 77 ;CHECK: vrev32.16
78 %tmp1 = load <4 x i16>* %A 78 %tmp1 = load <4 x i16>, <4 x i16>* %A
79 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> 79 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
80 ret <4 x i16> %tmp2 80 ret <4 x i16> %tmp2
81 } 81 }
82 82
83 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { 83 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
84 ;CHECK-LABEL: test_vrev32Q8: 84 ;CHECK-LABEL: test_vrev32Q8:
85 ;CHECK: vrev32.8 85 ;CHECK: vrev32.8
86 %tmp1 = load <16 x i8>* %A 86 %tmp1 = load <16 x i8>, <16 x i8>* %A
87 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> 87 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
88 ret <16 x i8> %tmp2 88 ret <16 x i8> %tmp2
89 } 89 }
90 90
91 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { 91 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
92 ;CHECK-LABEL: test_vrev32Q16: 92 ;CHECK-LABEL: test_vrev32Q16:
93 ;CHECK: vrev32.16 93 ;CHECK: vrev32.16
94 %tmp1 = load <8 x i16>* %A 94 %tmp1 = load <8 x i16>, <8 x i16>* %A
95 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> 95 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
96 ret <8 x i16> %tmp2 96 ret <8 x i16> %tmp2
97 } 97 }
98 98
99 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { 99 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
100 ;CHECK-LABEL: test_vrev16D8: 100 ;CHECK-LABEL: test_vrev16D8:
101 ;CHECK: vrev16.8 101 ;CHECK: vrev16.8
102 %tmp1 = load <8 x i8>* %A 102 %tmp1 = load <8 x i8>, <8 x i8>* %A
103 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> 103 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
104 ret <8 x i8> %tmp2 104 ret <8 x i8> %tmp2
105 } 105 }
106 106
107 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { 107 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
108 ;CHECK-LABEL: test_vrev16Q8: 108 ;CHECK-LABEL: test_vrev16Q8:
109 ;CHECK: vrev16.8 109 ;CHECK: vrev16.8
110 %tmp1 = load <16 x i8>* %A 110 %tmp1 = load <16 x i8>, <16 x i8>* %A
111 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> 111 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
112 ret <16 x i8> %tmp2 112 ret <16 x i8> %tmp2
113 } 113 }
114 114
115 ; Undef shuffle indices should not prevent matching to VREV: 115 ; Undef shuffle indices should not prevent matching to VREV:
116 116
117 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { 117 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
118 ;CHECK-LABEL: test_vrev64D8_undef: 118 ;CHECK-LABEL: test_vrev64D8_undef:
119 ;CHECK: vrev64.8 119 ;CHECK: vrev64.8
120 %tmp1 = load <8 x i8>* %A 120 %tmp1 = load <8 x i8>, <8 x i8>* %A
121 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0> 121 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
122 ret <8 x i8> %tmp2 122 ret <8 x i8> %tmp2
123 } 123 }
124 124
125 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind { 125 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
126 ;CHECK-LABEL: test_vrev32Q16_undef: 126 ;CHECK-LABEL: test_vrev32Q16_undef:
127 ;CHECK: vrev32.16 127 ;CHECK: vrev32.16
128 %tmp1 = load <8 x i16>* %A 128 %tmp1 = load <8 x i16>, <8 x i16>* %A
129 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef> 129 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
130 ret <8 x i16> %tmp2 130 ret <8 x i16> %tmp2
131 } 131 }
132 132
133 ; A vcombine feeding a VREV should not obscure things. Radar 8597007. 133 ; A vcombine feeding a VREV should not obscure things. Radar 8597007.
134 134
135 define void @test_with_vcombine(<4 x float>* %v) nounwind { 135 define void @test_with_vcombine(<4 x float>* %v) nounwind {
136 ;CHECK-LABEL: test_with_vcombine: 136 ;CHECK-LABEL: test_with_vcombine:
137 ;CHECK-NOT: vext 137 ;CHECK-NOT: vext
138 ;CHECK: vrev64.32 138 ;CHECK: vrev64.32
139 %tmp1 = load <4 x float>* %v, align 16 139 %tmp1 = load <4 x float>, <4 x float>* %v, align 16
140 %tmp2 = bitcast <4 x float> %tmp1 to <2 x double> 140 %tmp2 = bitcast <4 x float> %tmp1 to <2 x double>
141 %tmp3 = extractelement <2 x double> %tmp2, i32 0 141 %tmp3 = extractelement <2 x double> %tmp2, i32 0
142 %tmp4 = bitcast double %tmp3 to <2 x float> 142 %tmp4 = bitcast double %tmp3 to <2 x float>
143 %tmp5 = extractelement <2 x double> %tmp2, i32 1 143 %tmp5 = extractelement <2 x double> %tmp2, i32 1
144 %tmp6 = bitcast double %tmp5 to <2 x float> 144 %tmp6 = bitcast double %tmp5 to <2 x float>
153 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { 153 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
154 ; CHECK-LABEL: test_vrev64: 154 ; CHECK-LABEL: test_vrev64:
155 ; CHECK: vst1.32 155 ; CHECK: vst1.32
156 entry: 156 entry:
157 %0 = bitcast <4 x i16>* %source to <8 x i16>* 157 %0 = bitcast <4 x i16>* %source to <8 x i16>*
158 %tmp2 = load <8 x i16>* %0, align 4 158 %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4
159 %tmp3 = extractelement <8 x i16> %tmp2, i32 6 159 %tmp3 = extractelement <8 x i16> %tmp2, i32 6
160 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 160 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
161 %tmp9 = extractelement <8 x i16> %tmp2, i32 5 161 %tmp9 = extractelement <8 x i16> %tmp2, i32 5
162 %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1 162 %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
163 store <2 x i16> %tmp11, <2 x i16>* %dst, align 4 163 store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
169 ; CHECK: float_vrev64 169 ; CHECK: float_vrev64
170 ; CHECK: vext.32 170 ; CHECK: vext.32
171 ; CHECK: vrev64.32 171 ; CHECK: vrev64.32
172 entry: 172 entry:
173 %0 = bitcast float* %source to <4 x float>* 173 %0 = bitcast float* %source to <4 x float>*
174 %tmp2 = load <4 x float>* %0, align 4 174 %tmp2 = load <4 x float>, <4 x float>* %0, align 4
175 %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0> 175 %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
176 %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11 176 %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11
177 store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4 177 store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
178 ret void 178 ret void
179 } 179 }
180 180
181 define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind { 181 define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {