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comparison test/CodeGen/ARM/vshiftins.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children
comparison
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84:f3e34b893a5f 95:afa8332a0e37
1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
2 2
3 define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 3 define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
4 ;CHECK-LABEL: vsli8: 4 ;CHECK-LABEL: vsli8:
5 ;CHECK: vsli.8 5 ;CHECK: vsli.8
6 %tmp1 = load <8 x i8>* %A 6 %tmp1 = load <8 x i8>, <8 x i8>* %A
7 %tmp2 = load <8 x i8>* %B 7 %tmp2 = load <8 x i8>, <8 x i8>* %B
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) 8 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
9 ret <8 x i8> %tmp3 9 ret <8 x i8> %tmp3
10 } 10 }
11 11
12 define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 12 define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
13 ;CHECK-LABEL: vsli16: 13 ;CHECK-LABEL: vsli16:
14 ;CHECK: vsli.16 14 ;CHECK: vsli.16
15 %tmp1 = load <4 x i16>* %A 15 %tmp1 = load <4 x i16>, <4 x i16>* %A
16 %tmp2 = load <4 x i16>* %B 16 %tmp2 = load <4 x i16>, <4 x i16>* %B
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) 17 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
18 ret <4 x i16> %tmp3 18 ret <4 x i16> %tmp3
19 } 19 }
20 20
21 define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 21 define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
22 ;CHECK-LABEL: vsli32: 22 ;CHECK-LABEL: vsli32:
23 ;CHECK: vsli.32 23 ;CHECK: vsli.32
24 %tmp1 = load <2 x i32>* %A 24 %tmp1 = load <2 x i32>, <2 x i32>* %A
25 %tmp2 = load <2 x i32>* %B 25 %tmp2 = load <2 x i32>, <2 x i32>* %B
26 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >) 26 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 31, i32 31 >)
27 ret <2 x i32> %tmp3 27 ret <2 x i32> %tmp3
28 } 28 }
29 29
30 define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { 30 define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
31 ;CHECK-LABEL: vsli64: 31 ;CHECK-LABEL: vsli64:
32 ;CHECK: vsli.64 32 ;CHECK: vsli.64
33 %tmp1 = load <1 x i64>* %A 33 %tmp1 = load <1 x i64>, <1 x i64>* %A
34 %tmp2 = load <1 x i64>* %B 34 %tmp2 = load <1 x i64>, <1 x i64>* %B
35 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >) 35 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 63 >)
36 ret <1 x i64> %tmp3 36 ret <1 x i64> %tmp3
37 } 37 }
38 38
39 define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { 39 define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
40 ;CHECK-LABEL: vsliQ8: 40 ;CHECK-LABEL: vsliQ8:
41 ;CHECK: vsli.8 41 ;CHECK: vsli.8
42 %tmp1 = load <16 x i8>* %A 42 %tmp1 = load <16 x i8>, <16 x i8>* %A
43 %tmp2 = load <16 x i8>* %B 43 %tmp2 = load <16 x i8>, <16 x i8>* %B
44 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) 44 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
45 ret <16 x i8> %tmp3 45 ret <16 x i8> %tmp3
46 } 46 }
47 47
48 define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { 48 define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
49 ;CHECK-LABEL: vsliQ16: 49 ;CHECK-LABEL: vsliQ16:
50 ;CHECK: vsli.16 50 ;CHECK: vsli.16
51 %tmp1 = load <8 x i16>* %A 51 %tmp1 = load <8 x i16>, <8 x i16>* %A
52 %tmp2 = load <8 x i16>* %B 52 %tmp2 = load <8 x i16>, <8 x i16>* %B
53 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) 53 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
54 ret <8 x i16> %tmp3 54 ret <8 x i16> %tmp3
55 } 55 }
56 56
57 define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 57 define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
58 ;CHECK-LABEL: vsliQ32: 58 ;CHECK-LABEL: vsliQ32:
59 ;CHECK: vsli.32 59 ;CHECK: vsli.32
60 %tmp1 = load <4 x i32>* %A 60 %tmp1 = load <4 x i32>, <4 x i32>* %A
61 %tmp2 = load <4 x i32>* %B 61 %tmp2 = load <4 x i32>, <4 x i32>* %B
62 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) 62 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
63 ret <4 x i32> %tmp3 63 ret <4 x i32> %tmp3
64 } 64 }
65 65
66 define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { 66 define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
67 ;CHECK-LABEL: vsliQ64: 67 ;CHECK-LABEL: vsliQ64:
68 ;CHECK: vsli.64 68 ;CHECK: vsli.64
69 %tmp1 = load <2 x i64>* %A 69 %tmp1 = load <2 x i64>, <2 x i64>* %A
70 %tmp2 = load <2 x i64>* %B 70 %tmp2 = load <2 x i64>, <2 x i64>* %B
71 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >) 71 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
72 ret <2 x i64> %tmp3 72 ret <2 x i64> %tmp3
73 } 73 }
74 74
75 define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 75 define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
76 ;CHECK-LABEL: vsri8: 76 ;CHECK-LABEL: vsri8:
77 ;CHECK: vsri.8 77 ;CHECK: vsri.8
78 %tmp1 = load <8 x i8>* %A 78 %tmp1 = load <8 x i8>, <8 x i8>* %A
79 %tmp2 = load <8 x i8>* %B 79 %tmp2 = load <8 x i8>, <8 x i8>* %B
80 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) 80 %tmp3 = call <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
81 ret <8 x i8> %tmp3 81 ret <8 x i8> %tmp3
82 } 82 }
83 83
84 define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 84 define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
85 ;CHECK-LABEL: vsri16: 85 ;CHECK-LABEL: vsri16:
86 ;CHECK: vsri.16 86 ;CHECK: vsri.16
87 %tmp1 = load <4 x i16>* %A 87 %tmp1 = load <4 x i16>, <4 x i16>* %A
88 %tmp2 = load <4 x i16>* %B 88 %tmp2 = load <4 x i16>, <4 x i16>* %B
89 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) 89 %tmp3 = call <4 x i16> @llvm.arm.neon.vshiftins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
90 ret <4 x i16> %tmp3 90 ret <4 x i16> %tmp3
91 } 91 }
92 92
93 define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 93 define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
94 ;CHECK-LABEL: vsri32: 94 ;CHECK-LABEL: vsri32:
95 ;CHECK: vsri.32 95 ;CHECK: vsri.32
96 %tmp1 = load <2 x i32>* %A 96 %tmp1 = load <2 x i32>, <2 x i32>* %A
97 %tmp2 = load <2 x i32>* %B 97 %tmp2 = load <2 x i32>, <2 x i32>* %B
98 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >) 98 %tmp3 = call <2 x i32> @llvm.arm.neon.vshiftins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> < i32 -32, i32 -32 >)
99 ret <2 x i32> %tmp3 99 ret <2 x i32> %tmp3
100 } 100 }
101 101
102 define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { 102 define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
103 ;CHECK-LABEL: vsri64: 103 ;CHECK-LABEL: vsri64:
104 ;CHECK: vsri.64 104 ;CHECK: vsri.64
105 %tmp1 = load <1 x i64>* %A 105 %tmp1 = load <1 x i64>, <1 x i64>* %A
106 %tmp2 = load <1 x i64>* %B 106 %tmp2 = load <1 x i64>, <1 x i64>* %B
107 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >) 107 %tmp3 = call <1 x i64> @llvm.arm.neon.vshiftins.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, <1 x i64> < i64 -64 >)
108 ret <1 x i64> %tmp3 108 ret <1 x i64> %tmp3
109 } 109 }
110 110
111 define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { 111 define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
112 ;CHECK-LABEL: vsriQ8: 112 ;CHECK-LABEL: vsriQ8:
113 ;CHECK: vsri.8 113 ;CHECK: vsri.8
114 %tmp1 = load <16 x i8>* %A 114 %tmp1 = load <16 x i8>, <16 x i8>* %A
115 %tmp2 = load <16 x i8>* %B 115 %tmp2 = load <16 x i8>, <16 x i8>* %B
116 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) 116 %tmp3 = call <16 x i8> @llvm.arm.neon.vshiftins.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
117 ret <16 x i8> %tmp3 117 ret <16 x i8> %tmp3
118 } 118 }
119 119
120 define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { 120 define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
121 ;CHECK-LABEL: vsriQ16: 121 ;CHECK-LABEL: vsriQ16:
122 ;CHECK: vsri.16 122 ;CHECK: vsri.16
123 %tmp1 = load <8 x i16>* %A 123 %tmp1 = load <8 x i16>, <8 x i16>* %A
124 %tmp2 = load <8 x i16>* %B 124 %tmp2 = load <8 x i16>, <8 x i16>* %B
125 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) 125 %tmp3 = call <8 x i16> @llvm.arm.neon.vshiftins.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
126 ret <8 x i16> %tmp3 126 ret <8 x i16> %tmp3
127 } 127 }
128 128
129 define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 129 define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
130 ;CHECK-LABEL: vsriQ32: 130 ;CHECK-LABEL: vsriQ32:
131 ;CHECK: vsri.32 131 ;CHECK: vsri.32
132 %tmp1 = load <4 x i32>* %A 132 %tmp1 = load <4 x i32>, <4 x i32>* %A
133 %tmp2 = load <4 x i32>* %B 133 %tmp2 = load <4 x i32>, <4 x i32>* %B
134 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) 134 %tmp3 = call <4 x i32> @llvm.arm.neon.vshiftins.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
135 ret <4 x i32> %tmp3 135 ret <4 x i32> %tmp3
136 } 136 }
137 137
138 define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { 138 define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
139 ;CHECK-LABEL: vsriQ64: 139 ;CHECK-LABEL: vsriQ64:
140 ;CHECK: vsri.64 140 ;CHECK: vsri.64
141 %tmp1 = load <2 x i64>* %A 141 %tmp1 = load <2 x i64>, <2 x i64>* %A
142 %tmp2 = load <2 x i64>* %B 142 %tmp2 = load <2 x i64>, <2 x i64>* %B
143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >) 143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
144 ret <2 x i64> %tmp3 144 ret <2 x i64> %tmp3
145 } 145 }
146 146
147 declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone 147 declare <8 x i8> @llvm.arm.neon.vshiftins.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone