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comparison test/CodeGen/SystemZ/vec-move-02.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
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84:f3e34b893a5f 95:afa8332a0e37
1 ; Test vector loads.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5 ; Test v16i8 loads.
6 define <16 x i8> @f1(<16 x i8> *%ptr) {
7 ; CHECK-LABEL: f1:
8 ; CHECK: vl %v24, 0(%r2)
9 ; CHECK: br %r14
10 %ret = load <16 x i8>, <16 x i8> *%ptr
11 ret <16 x i8> %ret
12 }
13
14 ; Test v8i16 loads.
15 define <8 x i16> @f2(<8 x i16> *%ptr) {
16 ; CHECK-LABEL: f2:
17 ; CHECK: vl %v24, 0(%r2)
18 ; CHECK: br %r14
19 %ret = load <8 x i16>, <8 x i16> *%ptr
20 ret <8 x i16> %ret
21 }
22
23 ; Test v4i32 loads.
24 define <4 x i32> @f3(<4 x i32> *%ptr) {
25 ; CHECK-LABEL: f3:
26 ; CHECK: vl %v24, 0(%r2)
27 ; CHECK: br %r14
28 %ret = load <4 x i32>, <4 x i32> *%ptr
29 ret <4 x i32> %ret
30 }
31
32 ; Test v2i64 loads.
33 define <2 x i64> @f4(<2 x i64> *%ptr) {
34 ; CHECK-LABEL: f4:
35 ; CHECK: vl %v24, 0(%r2)
36 ; CHECK: br %r14
37 %ret = load <2 x i64>, <2 x i64> *%ptr
38 ret <2 x i64> %ret
39 }
40
41 ; Test v4f32 loads.
42 define <4 x float> @f5(<4 x float> *%ptr) {
43 ; CHECK-LABEL: f5:
44 ; CHECK: vl %v24, 0(%r2)
45 ; CHECK: br %r14
46 %ret = load <4 x float>, <4 x float> *%ptr
47 ret <4 x float> %ret
48 }
49
50 ; Test v2f64 loads.
51 define <2 x double> @f6(<2 x double> *%ptr) {
52 ; CHECK-LABEL: f6:
53 ; CHECK: vl %v24, 0(%r2)
54 ; CHECK: br %r14
55 %ret = load <2 x double>, <2 x double> *%ptr
56 ret <2 x double> %ret
57 }
58
59 ; Test the highest aligned in-range offset.
60 define <16 x i8> @f7(<16 x i8> *%base) {
61 ; CHECK-LABEL: f7:
62 ; CHECK: vl %v24, 4080(%r2)
63 ; CHECK: br %r14
64 %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
65 %ret = load <16 x i8>, <16 x i8> *%ptr
66 ret <16 x i8> %ret
67 }
68
69 ; Test the highest unaligned in-range offset.
70 define <16 x i8> @f8(i8 *%base) {
71 ; CHECK-LABEL: f8:
72 ; CHECK: vl %v24, 4095(%r2)
73 ; CHECK: br %r14
74 %addr = getelementptr i8, i8 *%base, i64 4095
75 %ptr = bitcast i8 *%addr to <16 x i8> *
76 %ret = load <16 x i8>, <16 x i8> *%ptr, align 1
77 ret <16 x i8> %ret
78 }
79
80 ; Test the next offset up, which requires separate address logic,
81 define <16 x i8> @f9(<16 x i8> *%base) {
82 ; CHECK-LABEL: f9:
83 ; CHECK: aghi %r2, 4096
84 ; CHECK: vl %v24, 0(%r2)
85 ; CHECK: br %r14
86 %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
87 %ret = load <16 x i8>, <16 x i8> *%ptr
88 ret <16 x i8> %ret
89 }
90
91 ; Test negative offsets, which also require separate address logic,
92 define <16 x i8> @f10(<16 x i8> *%base) {
93 ; CHECK-LABEL: f10:
94 ; CHECK: aghi %r2, -16
95 ; CHECK: vl %v24, 0(%r2)
96 ; CHECK: br %r14
97 %ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
98 %ret = load <16 x i8>, <16 x i8> *%ptr
99 ret <16 x i8> %ret
100 }
101
102 ; Check that indexes are allowed.
103 define <16 x i8> @f11(i8 *%base, i64 %index) {
104 ; CHECK-LABEL: f11:
105 ; CHECK: vl %v24, 0(%r3,%r2)
106 ; CHECK: br %r14
107 %addr = getelementptr i8, i8 *%base, i64 %index
108 %ptr = bitcast i8 *%addr to <16 x i8> *
109 %ret = load <16 x i8>, <16 x i8> *%ptr, align 1
110 ret <16 x i8> %ret
111 }
112
113 ; Test v2i8 loads.
114 define <2 x i8> @f12(<2 x i8> *%ptr) {
115 ; CHECK-LABEL: f12:
116 ; CHECK: vlreph %v24, 0(%r2)
117 ; CHECK: br %r14
118 %ret = load <2 x i8>, <2 x i8> *%ptr
119 ret <2 x i8> %ret
120 }
121
122 ; Test v4i8 loads.
123 define <4 x i8> @f13(<4 x i8> *%ptr) {
124 ; CHECK-LABEL: f13:
125 ; CHECK: vlrepf %v24, 0(%r2)
126 ; CHECK: br %r14
127 %ret = load <4 x i8>, <4 x i8> *%ptr
128 ret <4 x i8> %ret
129 }
130
131 ; Test v8i8 loads.
132 define <8 x i8> @f14(<8 x i8> *%ptr) {
133 ; CHECK-LABEL: f14:
134 ; CHECK: vlrepg %v24, 0(%r2)
135 ; CHECK: br %r14
136 %ret = load <8 x i8>, <8 x i8> *%ptr
137 ret <8 x i8> %ret
138 }
139
140 ; Test v2i16 loads.
141 define <2 x i16> @f15(<2 x i16> *%ptr) {
142 ; CHECK-LABEL: f15:
143 ; CHECK: vlrepf %v24, 0(%r2)
144 ; CHECK: br %r14
145 %ret = load <2 x i16>, <2 x i16> *%ptr
146 ret <2 x i16> %ret
147 }
148
149 ; Test v4i16 loads.
150 define <4 x i16> @f16(<4 x i16> *%ptr) {
151 ; CHECK-LABEL: f16:
152 ; CHECK: vlrepg %v24, 0(%r2)
153 ; CHECK: br %r14
154 %ret = load <4 x i16>, <4 x i16> *%ptr
155 ret <4 x i16> %ret
156 }
157
158 ; Test v2i32 loads.
159 define <2 x i32> @f17(<2 x i32> *%ptr) {
160 ; CHECK-LABEL: f17:
161 ; CHECK: vlrepg %v24, 0(%r2)
162 ; CHECK: br %r14
163 %ret = load <2 x i32>, <2 x i32> *%ptr
164 ret <2 x i32> %ret
165 }
166
167 ; Test v2f32 loads.
168 define <2 x float> @f18(<2 x float> *%ptr) {
169 ; CHECK-LABEL: f18:
170 ; CHECK: vlrepg %v24, 0(%r2)
171 ; CHECK: br %r14
172 %ret = load <2 x float>, <2 x float> *%ptr
173 ret <2 x float> %ret
174 }