Mercurial > hg > Members > tobaru > cbc > CbC_llvm
diff lib/Target/PowerPC/PPCInstrInfo.cpp @ 120:1172e4bd9c6f
update 4.0.0
| author | mir3636 |
|---|---|
| date | Fri, 25 Nov 2016 19:14:25 +0900 |
| parents | 7d135dc70f03 |
| children | 803732b1fca8 |
line wrap: on
line diff
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Jan 26 22:56:36 2016 +0900 +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Nov 25 19:14:25 2016 +0900 @@ -93,6 +93,7 @@ unsigned Directive = DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective(); + // FIXME: Leaving this as-is until we have POWER9 scheduling info if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) return new PPCDispatchGroupSBHazardRecognizer(II, DAG); @@ -108,7 +109,7 @@ } unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, - const MachineInstr *MI, + const MachineInstr &MI, unsigned *PredCost) const { if (!ItinData || UseOldLatencyCalc) return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); @@ -121,9 +122,9 @@ // is an output). unsigned Latency = 1; - unsigned DefClass = MI->getDesc().getSchedClass(); - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); + unsigned DefClass = MI.getDesc().getSchedClass(); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) continue; @@ -138,22 +139,22 @@ } int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const MachineInstr *DefMI, unsigned DefIdx, - const MachineInstr *UseMI, + const MachineInstr &DefMI, unsigned DefIdx, + const MachineInstr &UseMI, unsigned UseIdx) const { int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); - if (!DefMI->getParent()) + if (!DefMI.getParent()) return Latency; - const MachineOperand &DefMO = DefMI->getOperand(DefIdx); + const MachineOperand &DefMO = DefMI.getOperand(DefIdx); unsigned Reg = DefMO.getReg(); bool IsRegCR; if (TargetRegisterInfo::isVirtualRegister(Reg)) { const MachineRegisterInfo *MRI = - &DefMI->getParent()->getParent()->getRegInfo(); + &DefMI.getParent()->getParent()->getRegInfo(); IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); } else { @@ -161,7 +162,7 @@ PPC::CRBITRCRegClass.contains(Reg); } - if (UseMI->isBranch() && IsRegCR) { + if (UseMI.isBranch() && IsRegCR) { if (Latency < 0) Latency = getInstrLatency(ItinData, DefMI); @@ -181,6 +182,7 @@ case PPC::DIR_PWR6X: case PPC::DIR_PWR7: case PPC::DIR_PWR8: + // FIXME: Is this needed for POWER9? Latency += 2; break; } @@ -258,10 +260,10 @@ } } -unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, +unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { // Note: This list must be kept consistent with LoadRegFromStackSlot. - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: break; case PPC::LD: case PPC::LWZ: @@ -271,26 +273,27 @@ case PPC::RESTORE_CRBIT: case PPC::LVX: case PPC::LXVD2X: + case PPC::LXVX: case PPC::QVLFDX: case PPC::QVLFSXs: case PPC::QVLFDXb: case PPC::RESTORE_VRSAVE: // Check for the operands added by addFrameReference (the immediate is the // offset which defaults to 0). - if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && - MI->getOperand(2).isFI()) { - FrameIndex = MI->getOperand(2).getIndex(); - return MI->getOperand(0).getReg(); + if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() && + MI.getOperand(2).isFI()) { + FrameIndex = MI.getOperand(2).getIndex(); + return MI.getOperand(0).getReg(); } break; } return 0; } -unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, +unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { // Note: This list must be kept consistent with StoreRegToStackSlot. - switch (MI->getOpcode()) { + switch (MI.getOpcode()) { default: break; case PPC::STD: case PPC::STW: @@ -300,31 +303,30 @@ case PPC::SPILL_CRBIT: case PPC::STVX: case PPC::STXVD2X: + case PPC::STXVX: case PPC::QVSTFDX: case PPC::QVSTFSXs: case PPC::QVSTFDXb: case PPC::SPILL_VRSAVE: // Check for the operands added by addFrameReference (the immediate is the // offset which defaults to 0). - if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() && - MI->getOperand(2).isFI()) { - FrameIndex = MI->getOperand(2).getIndex(); - return MI->getOperand(0).getReg(); + if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() && + MI.getOperand(2).isFI()) { + FrameIndex = MI.getOperand(2).getIndex(); + return MI.getOperand(0).getReg(); } break; } return 0; } -MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr *MI, - bool NewMI, +MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const { - MachineFunction &MF = *MI->getParent()->getParent(); + MachineFunction &MF = *MI.getParent()->getParent(); // Normal instructions can be commuted the obvious way. - if (MI->getOpcode() != PPC::RLWIMI && - MI->getOpcode() != PPC::RLWIMIo) + if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo) return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because @@ -332,7 +334,7 @@ // to the high-bits of the mask (and, thus, the result). // Cannot commute if it has a non-zero rotate count. - if (MI->getOperand(3).getImm() != 0) + if (MI.getOperand(3).getImm() != 0) return nullptr; // If we have a zero rotate count, we have: @@ -345,28 +347,28 @@ // Swap op1/op2 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."); - unsigned Reg0 = MI->getOperand(0).getReg(); - unsigned Reg1 = MI->getOperand(1).getReg(); - unsigned Reg2 = MI->getOperand(2).getReg(); - unsigned SubReg1 = MI->getOperand(1).getSubReg(); - unsigned SubReg2 = MI->getOperand(2).getSubReg(); - bool Reg1IsKill = MI->getOperand(1).isKill(); - bool Reg2IsKill = MI->getOperand(2).isKill(); + unsigned Reg0 = MI.getOperand(0).getReg(); + unsigned Reg1 = MI.getOperand(1).getReg(); + unsigned Reg2 = MI.getOperand(2).getReg(); + unsigned SubReg1 = MI.getOperand(1).getSubReg(); + unsigned SubReg2 = MI.getOperand(2).getSubReg(); + bool Reg1IsKill = MI.getOperand(1).isKill(); + bool Reg2IsKill = MI.getOperand(2).isKill(); bool ChangeReg0 = false; // If machine instrs are no longer in two-address forms, update // destination register as well. if (Reg0 == Reg1) { // Must be two address instruction! - assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && + assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && "Expecting a two-address instruction!"); - assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); + assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"); Reg2IsKill = false; ChangeReg0 = true; } // Masks. - unsigned MB = MI->getOperand(4).getImm(); - unsigned ME = MI->getOperand(5).getImm(); + unsigned MB = MI.getOperand(4).getImm(); + unsigned ME = MI.getOperand(5).getImm(); // We can't commute a trivial mask (there is no way to represent an all-zero // mask). @@ -375,40 +377,40 @@ if (NewMI) { // Create a new instruction. - unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); - bool Reg0IsDead = MI->getOperand(0).isDead(); - return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) - .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) - .addReg(Reg2, getKillRegState(Reg2IsKill)) - .addReg(Reg1, getKillRegState(Reg1IsKill)) - .addImm((ME+1) & 31) - .addImm((MB-1) & 31); + unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); + bool Reg0IsDead = MI.getOperand(0).isDead(); + return BuildMI(MF, MI.getDebugLoc(), MI.getDesc()) + .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) + .addReg(Reg2, getKillRegState(Reg2IsKill)) + .addReg(Reg1, getKillRegState(Reg1IsKill)) + .addImm((ME + 1) & 31) + .addImm((MB - 1) & 31); } if (ChangeReg0) { - MI->getOperand(0).setReg(Reg2); - MI->getOperand(0).setSubReg(SubReg2); + MI.getOperand(0).setReg(Reg2); + MI.getOperand(0).setSubReg(SubReg2); } - MI->getOperand(2).setReg(Reg1); - MI->getOperand(1).setReg(Reg2); - MI->getOperand(2).setSubReg(SubReg1); - MI->getOperand(1).setSubReg(SubReg2); - MI->getOperand(2).setIsKill(Reg1IsKill); - MI->getOperand(1).setIsKill(Reg2IsKill); + MI.getOperand(2).setReg(Reg1); + MI.getOperand(1).setReg(Reg2); + MI.getOperand(2).setSubReg(SubReg1); + MI.getOperand(1).setSubReg(SubReg2); + MI.getOperand(2).setIsKill(Reg1IsKill); + MI.getOperand(1).setIsKill(Reg2IsKill); // Swap the mask around. - MI->getOperand(4).setImm((ME+1) & 31); - MI->getOperand(5).setImm((MB-1) & 31); - return MI; + MI.getOperand(4).setImm((ME + 1) & 31); + MI.getOperand(5).setImm((MB - 1) & 31); + return &MI; } -bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, +bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const { // For VSX A-Type FMA instructions, it is the first two operands that can be // commuted, however, because the non-encoded tied input operand is listed // first, the operands to swap are actually the second and third. - int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode()); + int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); if (AltOpc == -1) return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); @@ -428,6 +430,8 @@ case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */ + // FIXME: Update when POWER9 scheduling model is ready. + case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; } DebugLoc DL; @@ -442,7 +446,8 @@ // Branch analysis. // Note: If the condition register is set to CTR or CTR8 then this is a // BDNZ (imm == 1) or BDZ (imm == 0) branch. -bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, +bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { @@ -453,61 +458,61 @@ if (I == MBB.end()) return false; - if (!isUnpredicatedTerminator(I)) + if (!isUnpredicatedTerminator(*I)) return false; // Get the last instruction in the block. - MachineInstr *LastInst = I; + MachineInstr &LastInst = *I; // If there is only one terminator instruction, process it. - if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { - if (LastInst->getOpcode() == PPC::B) { - if (!LastInst->getOperand(0).isMBB()) + if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { + if (LastInst.getOpcode() == PPC::B) { + if (!LastInst.getOperand(0).isMBB()) return true; - TBB = LastInst->getOperand(0).getMBB(); + TBB = LastInst.getOperand(0).getMBB(); return false; - } else if (LastInst->getOpcode() == PPC::BCC) { - if (!LastInst->getOperand(2).isMBB()) + } else if (LastInst.getOpcode() == PPC::BCC) { + if (!LastInst.getOperand(2).isMBB()) return true; // Block ends with fall-through condbranch. - TBB = LastInst->getOperand(2).getMBB(); - Cond.push_back(LastInst->getOperand(0)); - Cond.push_back(LastInst->getOperand(1)); + TBB = LastInst.getOperand(2).getMBB(); + Cond.push_back(LastInst.getOperand(0)); + Cond.push_back(LastInst.getOperand(1)); return false; - } else if (LastInst->getOpcode() == PPC::BC) { - if (!LastInst->getOperand(1).isMBB()) + } else if (LastInst.getOpcode() == PPC::BC) { + if (!LastInst.getOperand(1).isMBB()) return true; // Block ends with fall-through condbranch. - TBB = LastInst->getOperand(1).getMBB(); + TBB = LastInst.getOperand(1).getMBB(); Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); - Cond.push_back(LastInst->getOperand(0)); + Cond.push_back(LastInst.getOperand(0)); return false; - } else if (LastInst->getOpcode() == PPC::BCn) { - if (!LastInst->getOperand(1).isMBB()) + } else if (LastInst.getOpcode() == PPC::BCn) { + if (!LastInst.getOperand(1).isMBB()) return true; // Block ends with fall-through condbranch. - TBB = LastInst->getOperand(1).getMBB(); + TBB = LastInst.getOperand(1).getMBB(); Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); - Cond.push_back(LastInst->getOperand(0)); + Cond.push_back(LastInst.getOperand(0)); return false; - } else if (LastInst->getOpcode() == PPC::BDNZ8 || - LastInst->getOpcode() == PPC::BDNZ) { - if (!LastInst->getOperand(0).isMBB()) + } else if (LastInst.getOpcode() == PPC::BDNZ8 || + LastInst.getOpcode() == PPC::BDNZ) { + if (!LastInst.getOperand(0).isMBB()) return true; if (DisableCTRLoopAnal) return true; - TBB = LastInst->getOperand(0).getMBB(); + TBB = LastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(1)); Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, true)); return false; - } else if (LastInst->getOpcode() == PPC::BDZ8 || - LastInst->getOpcode() == PPC::BDZ) { - if (!LastInst->getOperand(0).isMBB()) + } else if (LastInst.getOpcode() == PPC::BDZ8 || + LastInst.getOpcode() == PPC::BDZ) { + if (!LastInst.getOperand(0).isMBB()) return true; if (DisableCTRLoopAnal) return true; - TBB = LastInst->getOperand(0).getMBB(); + TBB = LastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, true)); @@ -519,81 +524,79 @@ } // Get the instruction before it if it's a terminator. - MachineInstr *SecondLastInst = I; + MachineInstr &SecondLastInst = *I; // If there are three terminators, we don't know what sort of block this is. - if (SecondLastInst && I != MBB.begin() && - isUnpredicatedTerminator(--I)) + if (I != MBB.begin() && isUnpredicatedTerminator(*--I)) return true; // If the block ends with PPC::B and PPC:BCC, handle it. - if (SecondLastInst->getOpcode() == PPC::BCC && - LastInst->getOpcode() == PPC::B) { - if (!SecondLastInst->getOperand(2).isMBB() || - !LastInst->getOperand(0).isMBB()) + if (SecondLastInst.getOpcode() == PPC::BCC && + LastInst.getOpcode() == PPC::B) { + if (!SecondLastInst.getOperand(2).isMBB() || + !LastInst.getOperand(0).isMBB()) return true; - TBB = SecondLastInst->getOperand(2).getMBB(); - Cond.push_back(SecondLastInst->getOperand(0)); - Cond.push_back(SecondLastInst->getOperand(1)); - FBB = LastInst->getOperand(0).getMBB(); + TBB = SecondLastInst.getOperand(2).getMBB(); + Cond.push_back(SecondLastInst.getOperand(0)); + Cond.push_back(SecondLastInst.getOperand(1)); + FBB = LastInst.getOperand(0).getMBB(); return false; - } else if (SecondLastInst->getOpcode() == PPC::BC && - LastInst->getOpcode() == PPC::B) { - if (!SecondLastInst->getOperand(1).isMBB() || - !LastInst->getOperand(0).isMBB()) + } else if (SecondLastInst.getOpcode() == PPC::BC && + LastInst.getOpcode() == PPC::B) { + if (!SecondLastInst.getOperand(1).isMBB() || + !LastInst.getOperand(0).isMBB()) return true; - TBB = SecondLastInst->getOperand(1).getMBB(); + TBB = SecondLastInst.getOperand(1).getMBB(); Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); - Cond.push_back(SecondLastInst->getOperand(0)); - FBB = LastInst->getOperand(0).getMBB(); + Cond.push_back(SecondLastInst.getOperand(0)); + FBB = LastInst.getOperand(0).getMBB(); return false; - } else if (SecondLastInst->getOpcode() == PPC::BCn && - LastInst->getOpcode() == PPC::B) { - if (!SecondLastInst->getOperand(1).isMBB() || - !LastInst->getOperand(0).isMBB()) + } else if (SecondLastInst.getOpcode() == PPC::BCn && + LastInst.getOpcode() == PPC::B) { + if (!SecondLastInst.getOperand(1).isMBB() || + !LastInst.getOperand(0).isMBB()) return true; - TBB = SecondLastInst->getOperand(1).getMBB(); + TBB = SecondLastInst.getOperand(1).getMBB(); Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); - Cond.push_back(SecondLastInst->getOperand(0)); - FBB = LastInst->getOperand(0).getMBB(); + Cond.push_back(SecondLastInst.getOperand(0)); + FBB = LastInst.getOperand(0).getMBB(); return false; - } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 || - SecondLastInst->getOpcode() == PPC::BDNZ) && - LastInst->getOpcode() == PPC::B) { - if (!SecondLastInst->getOperand(0).isMBB() || - !LastInst->getOperand(0).isMBB()) + } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 || + SecondLastInst.getOpcode() == PPC::BDNZ) && + LastInst.getOpcode() == PPC::B) { + if (!SecondLastInst.getOperand(0).isMBB() || + !LastInst.getOperand(0).isMBB()) return true; if (DisableCTRLoopAnal) return true; - TBB = SecondLastInst->getOperand(0).getMBB(); + TBB = SecondLastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(1)); Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, true)); - FBB = LastInst->getOperand(0).getMBB(); + FBB = LastInst.getOperand(0).getMBB(); return false; - } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 || - SecondLastInst->getOpcode() == PPC::BDZ) && - LastInst->getOpcode() == PPC::B) { - if (!SecondLastInst->getOperand(0).isMBB() || - !LastInst->getOperand(0).isMBB()) + } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 || + SecondLastInst.getOpcode() == PPC::BDZ) && + LastInst.getOpcode() == PPC::B) { + if (!SecondLastInst.getOperand(0).isMBB() || + !LastInst.getOperand(0).isMBB()) return true; if (DisableCTRLoopAnal) return true; - TBB = SecondLastInst->getOperand(0).getMBB(); + TBB = SecondLastInst.getOperand(0).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, true)); - FBB = LastInst->getOperand(0).getMBB(); + FBB = LastInst.getOperand(0).getMBB(); return false; } // If the block ends with two PPC:Bs, handle it. The second one is not // executed, so remove it. - if (SecondLastInst->getOpcode() == PPC::B && - LastInst->getOpcode() == PPC::B) { - if (!SecondLastInst->getOperand(0).isMBB()) + if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) { + if (!SecondLastInst.getOperand(0).isMBB()) return true; - TBB = SecondLastInst->getOperand(0).getMBB(); + TBB = SecondLastInst.getOperand(0).getMBB(); I = LastInst; if (AllowModify) I->eraseFromParent(); @@ -604,7 +607,10 @@ return true; } -unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) return 0; @@ -633,15 +639,17 @@ return 2; } -unsigned -PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - ArrayRef<MachineOperand> Cond, - DebugLoc DL) const { +unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef<MachineOperand> Cond, + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. - assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "PPC branch conditions have two components!"); + assert(!BytesAdded && "code size not handled"); bool isPPC64 = Subtarget.isPPC64(); @@ -721,9 +729,10 @@ } void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, DebugLoc dl, - unsigned DestReg, ArrayRef<MachineOperand> Cond, - unsigned TrueReg, unsigned FalseReg) const { + MachineBasicBlock::iterator MI, + const DebugLoc &dl, unsigned DestReg, + ArrayRef<MachineOperand> Cond, unsigned TrueReg, + unsigned FalseReg) const { assert(Cond.size() == 2 && "PPC branch conditions have two components!"); @@ -835,9 +844,9 @@ } void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const { + MachineBasicBlock::iterator I, + const DebugLoc &DL, unsigned DestReg, + unsigned SrcReg, bool KillSrc) const { // We can end up with self copies and similar things as a result of VSX copy // legalization. Promote them here. const TargetRegisterInfo *TRI = &getRegisterInfo(); @@ -850,15 +859,6 @@ llvm_unreachable("nop VSX copy"); DestReg = SuperReg; - } else if (PPC::VRRCRegClass.contains(DestReg) && - PPC::VSRCRegClass.contains(SrcReg)) { - unsigned SuperReg = - TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); - - if (VSXSelfCopyCrash && SrcReg == SuperReg) - llvm_unreachable("nop VSX copy"); - - DestReg = SuperReg; } else if (PPC::F8RCRegClass.contains(SrcReg) && PPC::VSRCRegClass.contains(DestReg)) { unsigned SuperReg = @@ -868,23 +868,14 @@ llvm_unreachable("nop VSX copy"); SrcReg = SuperReg; - } else if (PPC::VRRCRegClass.contains(SrcReg) && - PPC::VSRCRegClass.contains(DestReg)) { - unsigned SuperReg = - TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass); - - if (VSXSelfCopyCrash && DestReg == SuperReg) - llvm_unreachable("nop VSX copy"); - - SrcReg = SuperReg; } // Different class register copy if (PPC::CRBITRCRegClass.contains(SrcReg) && PPC::GPRCRegClass.contains(DestReg)) { unsigned CRReg = getCRFromCRBit(SrcReg); - BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg) - .addReg(CRReg), getKillRegState(KillSrc); + BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); + getKillRegState(KillSrc); // Rotate the CR bit in the CR fields to be the least significant bit and // then mask with 0x1 (MB = ME = 31). BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) @@ -895,13 +886,13 @@ return; } else if (PPC::CRRCRegClass.contains(SrcReg) && PPC::G8RCRegClass.contains(DestReg)) { - BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg) - .addReg(SrcReg), getKillRegState(KillSrc); + BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg); + getKillRegState(KillSrc); return; } else if (PPC::CRRCRegClass.contains(SrcReg) && PPC::GPRCRegClass.contains(DestReg)) { - BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg) - .addReg(SrcReg), getKillRegState(KillSrc); + BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg); + getKillRegState(KillSrc); return; } @@ -1001,19 +992,22 @@ FrameIdx)); NonRI = true; } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X)) + unsigned Op = Subtarget.hasP9Vector() ? PPC::STXVX : PPC::STXVD2X; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op)) .addReg(SrcReg, getKillRegState(isKill)), FrameIdx)); NonRI = true; } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX)) + unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)), FrameIdx)); NonRI = true; } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX)) + unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc)) .addReg(SrcReg, getKillRegState(isKill)), FrameIdx)); @@ -1063,6 +1057,15 @@ PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); FuncInfo->setHasSpills(); + // We need to avoid a situation in which the value from a VRRC register is + // spilled using an Altivec instruction and reloaded into a VSRC register + // using a VSX instruction. The issue with this is that the VSX + // load/store instructions swap the doublewords in the vector and the Altivec + // ones don't. The register classes on the spill/reload may be different if + // the register is defined using an Altivec instruction and is then used by a + // VSX instruction. + RC = updatedRC(RC); + bool NonRI = false, SpillsVRS = false; if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, NonRI, SpillsVRS)) @@ -1077,7 +1080,7 @@ for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); - const MachineFrameInfo &MFI = *MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FrameIdx), MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx), @@ -1085,12 +1088,11 @@ NewMIs.back()->addMemOperand(MF, MMO); } -bool -PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs, - bool &NonRI, bool &SpillsVRS) const{ +bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr *> &NewMIs, + bool &NonRI, bool &SpillsVRS) const { // Note: If additional load instructions are added here, // update isLoadFromStackSlot. @@ -1123,16 +1125,19 @@ FrameIdx)); NonRI = true; } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg), + unsigned Op = Subtarget.hasP9Vector() ? PPC::LXVX : PPC::LXVD2X; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg), FrameIdx)); NonRI = true; } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg), - FrameIdx)); + unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc), + DestReg), FrameIdx)); NonRI = true; } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { - NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg), - FrameIdx)); + unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX; + NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc), + DestReg), FrameIdx)); NonRI = true; } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { assert(Subtarget.isDarwin() && @@ -1175,6 +1180,16 @@ PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); FuncInfo->setHasSpills(); + // We need to avoid a situation in which the value from a VRRC register is + // spilled using an Altivec instruction and reloaded into a VSRC register + // using a VSX instruction. The issue with this is that the VSX + // load/store instructions swap the doublewords in the vector and the Altivec + // ones don't. The register classes on the spill/reload may be different if + // the register is defined using an Altivec instruction and is then used by a + // VSX instruction. + if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) + RC = &PPC::VSRCRegClass; + bool NonRI = false, SpillsVRS = false; if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, NonRI, SpillsVRS)) @@ -1189,7 +1204,7 @@ for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); - const MachineFrameInfo &MFI = *MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo::getFixedStack(MF, FrameIdx), MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx), @@ -1198,7 +1213,7 @@ } bool PPCInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); @@ -1208,35 +1223,35 @@ return false; } -bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, - unsigned Reg, MachineRegisterInfo *MRI) const { +bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, + unsigned Reg, MachineRegisterInfo *MRI) const { // For some instructions, it is legal to fold ZERO into the RA register field. // A zero immediate should always be loaded with a single li. - unsigned DefOpc = DefMI->getOpcode(); + unsigned DefOpc = DefMI.getOpcode(); if (DefOpc != PPC::LI && DefOpc != PPC::LI8) return false; - if (!DefMI->getOperand(1).isImm()) + if (!DefMI.getOperand(1).isImm()) return false; - if (DefMI->getOperand(1).getImm() != 0) + if (DefMI.getOperand(1).getImm() != 0) return false; // Note that we cannot here invert the arguments of an isel in order to fold // a ZERO into what is presented as the second argument. All we have here // is the condition bit, and that might come from a CR-logical bit operation. - const MCInstrDesc &UseMCID = UseMI->getDesc(); + const MCInstrDesc &UseMCID = UseMI.getDesc(); // Only fold into real machine instructions. if (UseMCID.isPseudo()) return false; unsigned UseIdx; - for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx) - if (UseMI->getOperand(UseIdx).isReg() && - UseMI->getOperand(UseIdx).getReg() == Reg) + for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx) + if (UseMI.getOperand(UseIdx).isReg() && + UseMI.getOperand(UseIdx).getReg() == Reg) break; - assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI"); + assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; @@ -1268,10 +1283,10 @@ } bool DeleteDef = MRI->hasOneNonDBGUse(Reg); - UseMI->getOperand(UseIdx).setReg(ZeroReg); + UseMI.getOperand(UseIdx).setReg(ZeroReg); if (DeleteDef) - DefMI->eraseFromParent(); + DefMI.eraseFromParent(); return true; } @@ -1299,7 +1314,7 @@ } -bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const { +bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const { // The predicated branches are identified by their type, not really by the // explicit presence of a predicate. Furthermore, some of them can be // predicated more than once. Because if conversion won't try to predicate @@ -1310,73 +1325,71 @@ return false; } -bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - if (!MI->isTerminator()) +bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const { + if (!MI.isTerminator()) return false; // Conditional branch is a special case. - if (MI->isBranch() && !MI->isBarrier()) + if (MI.isBranch() && !MI.isBarrier()) return true; return !isPredicated(MI); } -bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI, +bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, ArrayRef<MachineOperand> Pred) const { - unsigned OpC = MI->getOpcode(); + unsigned OpC = MI.getOpcode(); if (OpC == PPC::BLR || OpC == PPC::BLR8) { if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { bool isPPC64 = Subtarget.isPPC64(); - MI->setDesc(get(Pred[0].getImm() ? - (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) : - (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); + MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) + : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { - MI->setDesc(get(PPC::BCLR)); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addReg(Pred[1].getReg()); + MI.setDesc(get(PPC::BCLR)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addReg(Pred[1].getReg()); } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { - MI->setDesc(get(PPC::BCLRn)); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addReg(Pred[1].getReg()); + MI.setDesc(get(PPC::BCLRn)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addReg(Pred[1].getReg()); } else { - MI->setDesc(get(PPC::BCCLR)); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addImm(Pred[0].getImm()) - .addReg(Pred[1].getReg()); + MI.setDesc(get(PPC::BCCLR)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addImm(Pred[0].getImm()) + .addReg(Pred[1].getReg()); } return true; } else if (OpC == PPC::B) { if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { bool isPPC64 = Subtarget.isPPC64(); - MI->setDesc(get(Pred[0].getImm() ? - (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : - (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); + MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) + : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { - MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); - MI->RemoveOperand(0); + MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); + MI.RemoveOperand(0); - MI->setDesc(get(PPC::BC)); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addReg(Pred[1].getReg()) - .addMBB(MBB); + MI.setDesc(get(PPC::BC)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addReg(Pred[1].getReg()) + .addMBB(MBB); } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { - MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); - MI->RemoveOperand(0); + MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); + MI.RemoveOperand(0); - MI->setDesc(get(PPC::BCn)); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addReg(Pred[1].getReg()) - .addMBB(MBB); + MI.setDesc(get(PPC::BCn)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addReg(Pred[1].getReg()) + .addMBB(MBB); } else { - MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); - MI->RemoveOperand(0); + MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); + MI.RemoveOperand(0); - MI->setDesc(get(PPC::BCC)); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addImm(Pred[0].getImm()) - .addReg(Pred[1].getReg()) - .addMBB(MBB); + MI.setDesc(get(PPC::BCC)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addImm(Pred[0].getImm()) + .addReg(Pred[1].getReg()) + .addMBB(MBB); } return true; @@ -1389,24 +1402,24 @@ bool isPPC64 = Subtarget.isPPC64(); if (Pred[0].getImm() == PPC::PRED_BIT_SET) { - MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) : - (setLR ? PPC::BCCTRL : PPC::BCCTR))); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addReg(Pred[1].getReg()); + MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) + : (setLR ? PPC::BCCTRL : PPC::BCCTR))); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addReg(Pred[1].getReg()); return true; } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { - MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) : - (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addReg(Pred[1].getReg()); + MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) + : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addReg(Pred[1].getReg()); return true; } - MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) : - (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); - MachineInstrBuilder(*MI->getParent()->getParent(), MI) - .addImm(Pred[0].getImm()) - .addReg(Pred[1].getReg()); + MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) + : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addImm(Pred[0].getImm()) + .addReg(Pred[1].getReg()); return true; } @@ -1444,7 +1457,7 @@ return false; } -bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI, +bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred) const { // Note: At the present time, the contents of Pred from this function is // unused by IfConversion. This implementation follows ARM by pushing the @@ -1457,8 +1470,8 @@ &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; bool Found = false; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) { const TargetRegisterClass *RC = RCs[c]; if (MO.isReg()) { @@ -1480,8 +1493,8 @@ return Found; } -bool PPCInstrInfo::isPredicable(MachineInstr *MI) const { - unsigned OpC = MI->getOpcode(); +bool PPCInstrInfo::isPredicable(MachineInstr &MI) const { + unsigned OpC = MI.getOpcode(); switch (OpC) { default: return false; @@ -1496,10 +1509,10 @@ } } -bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI, - unsigned &SrcReg, unsigned &SrcReg2, - int &Mask, int &Value) const { - unsigned Opc = MI->getOpcode(); +bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, + unsigned &SrcReg2, int &Mask, + int &Value) const { + unsigned Opc = MI.getOpcode(); switch (Opc) { default: return false; @@ -1507,9 +1520,9 @@ case PPC::CMPLWI: case PPC::CMPDI: case PPC::CMPLDI: - SrcReg = MI->getOperand(1).getReg(); + SrcReg = MI.getOperand(1).getReg(); SrcReg2 = 0; - Value = MI->getOperand(2).getImm(); + Value = MI.getOperand(2).getImm(); Mask = 0xFFFF; return true; case PPC::CMPW: @@ -1518,21 +1531,20 @@ case PPC::CMPLD: case PPC::FCMPUS: case PPC::FCMPUD: - SrcReg = MI->getOperand(1).getReg(); - SrcReg2 = MI->getOperand(2).getReg(); + SrcReg = MI.getOperand(1).getReg(); + SrcReg2 = MI.getOperand(2).getReg(); return true; } } -bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr, - unsigned SrcReg, unsigned SrcReg2, - int Mask, int Value, +bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, + unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const { if (DisableCmpOpt) return false; - int OpC = CmpInstr->getOpcode(); - unsigned CRReg = CmpInstr->getOperand(0).getReg(); + int OpC = CmpInstr.getOpcode(); + unsigned CRReg = CmpInstr.getOperand(0).getReg(); // FP record forms set CR1 based on the execption status bits, not a // comparison with zero. @@ -1571,11 +1583,18 @@ } else return false; } else if (is32BitUnsignedCompare) { + // 32-bit rotate and mask instructions are zero extending only if MB <= ME + bool isZeroExtendingRotate = + (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo || + MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo) + && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm(); + // We can perform this optimization, equality only, if MI is // zero-extending. if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo || MIOpC == PPC::SLW || MIOpC == PPC::SLWo || - MIOpC == PPC::SRW || MIOpC == PPC::SRWo) { + MIOpC == PPC::SRW || MIOpC == PPC::SRWo || + isZeroExtendingRotate) { noSub = true; equalityOnly = true; } else @@ -1608,8 +1627,8 @@ MachineBasicBlock::iterator I = CmpInstr; // Scan forward to find the first use of the compare. - for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end(); - I != EL; ++I) { + for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL; + ++I) { bool FoundUse = false; for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end(); J != JE; ++J) @@ -1633,7 +1652,7 @@ // same BB as the comparison. This is to allow the check below to avoid calls // (and other explicit clobbers); instead we should really check for these // more explicitly (in at least a few predecessors). - else if (MI->getParent() != CmpInstr->getParent() || Value != 0) { + else if (MI->getParent() != CmpInstr.getParent() || Value != 0) { // PPC does not have a record-form SUBri. return false; } @@ -1643,16 +1662,14 @@ --I; // Get ready to iterate backward from CmpInstr. - MachineBasicBlock::iterator E = MI, - B = CmpInstr->getParent()->begin(); + MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin(); for (; I != E && !noSub; --I) { const MachineInstr &Instr = *I; unsigned IOpC = Instr.getOpcode(); - if (&*I != CmpInstr && ( - Instr.modifiesRegister(PPC::CR0, TRI) || - Instr.readsRegister(PPC::CR0, TRI))) + if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || + Instr.readsRegister(PPC::CR0, TRI))) // This instruction modifies or uses the record condition register after // the one we want to change. While we could do this transformation, it // would likely not be profitable. This transformation removes one @@ -1752,13 +1769,17 @@ // Create a new virtual register to hold the value of the CR set by the // record-form instruction. If the instruction was not previously in // record form, then set the kill flag on the CR. - CmpInstr->eraseFromParent(); + CmpInstr.eraseFromParent(); MachineBasicBlock::iterator MII = MI; BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(), get(TargetOpcode::COPY), CRReg) .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); + // Even if CR0 register were dead before, it is alive now since the + // instruction we just built uses it. + MI->clearRegisterDeads(PPC::CR0); + if (MIOpC != NewOpC) { // We need to be careful here: we're replacing one instruction with // another, and we need to make sure that we get all of the right @@ -1783,6 +1804,8 @@ MI->addOperand(*MI->getParent()->getParent(), MachineOperand::CreateReg(*ImpUses, false, true)); } + assert(MI->definesRegister(PPC::CR0) && + "Record-form instruction does not define cr0?"); // Modify the condition code of operands in OperandsToUpdate. // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to @@ -1799,18 +1822,19 @@ /// GetInstSize - Return the number of bytes of code the specified /// instruction may be. This returns the maximum number of bytes. /// -unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { - unsigned Opcode = MI->getOpcode(); +unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { + unsigned Opcode = MI.getOpcode(); if (Opcode == PPC::INLINEASM) { - const MachineFunction *MF = MI->getParent()->getParent(); - const char *AsmStr = MI->getOperand(0).getSymbolName(); + const MachineFunction *MF = MI.getParent()->getParent(); + const char *AsmStr = MI.getOperand(0).getSymbolName(); return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); } else if (Opcode == TargetOpcode::STACKMAP) { - return MI->getOperand(1).getImm(); + StackMapOpers Opers(&MI); + return Opers.getNumPatchBytes(); } else if (Opcode == TargetOpcode::PATCHPOINT) { - PatchPointOpers Opers(MI); - return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); + PatchPointOpers Opers(&MI); + return Opers.getNumPatchBytes(); } else { const MCInstrDesc &Desc = get(Opcode); return Desc.getSize(); @@ -1842,10 +1866,68 @@ PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { using namespace PPCII; static const std::pair<unsigned, const char *> TargetFlags[] = { - {MO_PLT_OR_STUB, "ppc-plt-or-stub"}, + {MO_PLT, "ppc-plt"}, {MO_PIC_FLAG, "ppc-pic"}, {MO_NLP_FLAG, "ppc-nlp"}, {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}}; return makeArrayRef(TargetFlags); } +bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { + switch (MI.getOpcode()) { + case TargetOpcode::LOAD_STACK_GUARD: { + assert(Subtarget.isTargetLinux() && + "Only Linux target is expected to contain LOAD_STACK_GUARD"); + const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008; + const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; + MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); + MachineInstrBuilder(*MI.getParent()->getParent(), MI) + .addImm(Offset) + .addReg(Reg); + return true; + } + case PPC::DFLOADf32: + case PPC::DFLOADf64: + case PPC::DFSTOREf32: + case PPC::DFSTOREf64: { + assert(Subtarget.hasP9Vector() && + "Invalid D-Form Pseudo-ops on non-P9 target."); + unsigned UpperOpcode, LowerOpcode; + switch (MI.getOpcode()) { + case PPC::DFLOADf32: + UpperOpcode = PPC::LXSSP; + LowerOpcode = PPC::LFS; + break; + case PPC::DFLOADf64: + UpperOpcode = PPC::LXSD; + LowerOpcode = PPC::LFD; + break; + case PPC::DFSTOREf32: + UpperOpcode = PPC::STXSSP; + LowerOpcode = PPC::STFS; + break; + case PPC::DFSTOREf64: + UpperOpcode = PPC::STXSD; + LowerOpcode = PPC::STFD; + break; + } + unsigned TargetReg = MI.getOperand(0).getReg(); + unsigned Opcode; + if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || + (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) + Opcode = LowerOpcode; + else + Opcode = UpperOpcode; + MI.setDesc(get(Opcode)); + return true; + } + } + return false; +} + +const TargetRegisterClass * +PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const { + if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) + return &PPC::VSRCRegClass; + return RC; +}