Mercurial > hg > Members > tobaru > cbc > CbC_llvm
diff lib/Target/X86/X86InstrInfo.h @ 83:60c9769439b8
LLVM 3.7
author | Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp> |
---|---|
date | Wed, 18 Feb 2015 14:55:36 +0900 (2015-02-18) |
parents | 54457678186b |
children | afa8332a0e37 |
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--- a/lib/Target/X86/X86InstrInfo.h Mon Sep 08 22:07:30 2014 +0900 +++ b/lib/Target/X86/X86InstrInfo.h Wed Feb 18 14:55:36 2015 +0900 @@ -152,6 +152,7 @@ RegOp2MemOpTableType RegOp2MemOpTable1; RegOp2MemOpTableType RegOp2MemOpTable2; RegOp2MemOpTableType RegOp2MemOpTable3; + RegOp2MemOpTableType RegOp2MemOpTable4; /// MemOp2RegOpTable - Load / store unfolding opcode map. /// @@ -174,6 +175,11 @@ /// const X86RegisterInfo &getRegisterInfo() const { return RI; } + /// getSPAdjust - This returns the stack pointer adjustment made by + /// this instruction. For x86, we need to handle more complex call + /// sequences involving PUSHes. + int getSPAdjust(const MachineInstr *MI) const override; + /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" /// extension instruction. That is, it's like a copy where it's legal for the /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns @@ -404,7 +410,8 @@ MachineInstr* MI, unsigned OpNum, const SmallVectorImpl<MachineOperand> &MOs, - unsigned Size, unsigned Alignment) const; + unsigned Size, unsigned Alignment, + bool AllowCommute) const; void getUnconditionalBranch(MCInst &Branch, @@ -412,6 +419,8 @@ void getTrap(MCInst &MI) const override; + unsigned getJumpInstrTableEntryBound() const override; + bool isHighLatencyDef(int opc) const override; bool hasHighOperandLatency(const InstrItineraryData *ItinData,