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view test/CodeGen/X86/2011-12-15-vec_shift.ll @ 0:95c75e76d11b

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children afa8332a0e37
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; RUN: llc -march=x86-64 -mattr=+sse4.1 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-W-SSE4
; RUN: llc -march=x86-64 -mattr=-sse4.1 -mcpu=penryn < %s | FileCheck %s -check-prefix=CHECK-WO-SSE4
; Test case for r146671
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.7"

define <16 x i8> @shift(<16 x i8> %a, <16 x i8> %b) nounwind {
  ; Make sure operands to pblend are in the right order.
  ; CHECK-W-SSE4: psllw $4, [[REG1:%xmm.]]
  ; CHECK-W-SSE4: pblendvb [[REG1]],{{ %xmm.}}
  ; CHECK-W-SSE4: psllw $2

  ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
  ; CHECK-WO-SSE4: psllw $5, [[REG1:%xmm.]]
  ; CHECK-WO-SSE4: pand [[REG1]], [[REG2:%xmm.]]
  ; CHECK-WO-SSE4: pcmpeqb {{%xmm., }}[[REG2]]
  %1 = shl <16 x i8> %a, %b
  ret <16 x i8> %1
}