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view test/CodeGen/Hexagon/vect/vect-vsubw.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
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; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vsubw

define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind {
entry:
	%0 = sub <2 x i32> %a, %b
	ret <2 x i32> %0
}