Mercurial > hg > Papers > 2015 > yuhi-master
annotate paper/master_paper.toc @ 67:a63c2d9d7db9
fix slide
author | Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp> |
---|---|
date | Wed, 18 Feb 2015 08:29:48 +0900 |
parents | 48db1f674a83 |
children |
rev | line source |
---|---|
55 | 1 \contentsline {chapter}{\numberline {第1章}マルチプラットフォームな\\フレームワークにおける\\並列プログラミング}{1} |
2 \contentsline {chapter}{\numberline {第2章}既存のマルチプラットフォーム\\フレームワーク}{3} | |
33
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
3 \contentsline {section}{\numberline {2.1}GPU/Cell の Architecture}{3} |
31 | 4 \contentsline {section}{\numberline {2.2}OpenCL}{5} |
33
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
5 \contentsline {section}{\numberline {2.3}CUDA}{6} |
31 | 6 \contentsline {section}{\numberline {2.4}StarPU}{6} |
33
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
7 \contentsline {section}{\numberline {2.5}Cell Broadband Engine}{7} |
55 | 8 \contentsline {chapter}{\numberline {第3章}並列プログラミング\\フレームワーク Cerium}{8} |
33
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
9 \contentsline {section}{\numberline {3.1}Cerium の概要}{8} |
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
10 \contentsline {section}{\numberline {3.2}Cerium TaskManager}{8} |
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
11 \contentsline {section}{\numberline {3.3}Cerium における Task}{10} |
417431560eed
benchmark data parallel
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
32
diff
changeset
|
12 \contentsline {section}{\numberline {3.4}Task の Scheduling}{11} |
49
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
13 \contentsline {chapter}{\numberline {第4章}Cerium を用いた例題}{13} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
14 \contentsline {section}{\numberline {4.1}Bitonic Sort}{13} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
15 \contentsline {section}{\numberline {4.2}Word Count}{15} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
16 \contentsline {section}{\numberline {4.3}FFT}{17} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
17 \contentsline {section}{\numberline {4.4}Task の生成}{17} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
18 \contentsline {chapter}{\numberline {第5章}マルチコアへの対応}{20} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
19 \contentsline {section}{\numberline {5.1}マルチコア上での実行の機構}{20} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
20 \contentsline {section}{\numberline {5.2}DMA}{20} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
21 \contentsline {section}{\numberline {5.3}データ並列}{20} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
22 \contentsline {chapter}{\numberline {第6章}GPGPU への対応}{23} |
c7678996940c
add pipeline in multicore
Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
parents:
48
diff
changeset
|
23 \contentsline {section}{\numberline {6.1}OpenCL および CUDA による実装}{23} |
50 | 24 \contentsline {section}{\numberline {6.2}データ並列}{26} |
25 \contentsline {chapter}{\numberline {第7章}並列処理向けI/O}{28} | |
26 \contentsline {section}{\numberline {7.1}mmap}{28} | |
27 \contentsline {section}{\numberline {7.2}Blocked Read による I/O の並列化}{29} | |
28 \contentsline {section}{\numberline {7.3}I/O 専用 Thread の実装}{31} | |
29 \contentsline {chapter}{\numberline {第8章}ベンチマーク}{32} | |
30 \contentsline {section}{\numberline {8.1}実験環境}{32} | |
31 \contentsline {section}{\numberline {8.2}マルチコア}{33} | |
32 \contentsline {section}{\numberline {8.3}GPGPU}{35} | |
33 \contentsline {section}{\numberline {8.4}並列 I/O}{37} | |
34 \contentsline {chapter}{\numberline {第9章}既存のプログラミングフレームワークとの比較}{39} | |
35 \contentsline {section}{\numberline {9.1}OpenCL}{39} | |
36 \contentsline {section}{\numberline {9.2}CUDA}{40} | |
37 \contentsline {section}{\numberline {9.3}StarPU}{41} | |
38 \contentsline {chapter}{\numberline {第10章}結論}{43} | |
39 \contentsline {section}{\numberline {10.1}今後の課題}{44} | |
40 \contentsline {chapter}{謝辞}{45} | |
41 \contentsline {chapter}{参考文献}{46} | |
42 \contentsline {chapter}{発表文献}{47} |