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benchmark data parallel
author Yuhi TOMARI <yuhi@cr.ie.u-ryukyu.ac.jp>
date Sun, 15 Feb 2015 11:59:06 +0900
parents 9b7ce931cad9
children 9b181351ca4d
files paper/chapter1.tex paper/chapter4.tex paper/figures/GPU/.DS_Store paper/figures/GPU/fft/bar_plot.sh paper/graffle/wordcount.graffle paper/images/cell_arch.xbb paper/images/cpu_arch.pdf paper/images/cpu_arch.xbb paper/images/wordcount.pdf paper/master_paper.aux paper/master_paper.dvi paper/master_paper.lof paper/master_paper.log paper/master_paper.lot paper/master_paper.pdf paper/master_paper.toc
diffstat 16 files changed, 314 insertions(+), 492 deletions(-) [+]
line wrap: on
line diff
--- a/paper/chapter1.tex	Sat Feb 14 15:50:18 2015 +0900
+++ b/paper/chapter1.tex	Sun Feb 15 11:59:06 2015 +0900
@@ -3,7 +3,7 @@
 マルチプラットフォームにはマルチコア CPU 、 GPU や Cell といったヘテロジニアスマルチコアのような
 様々な構成がある。
 
-\section{GPU の Architecture}
+\section{GPU/Cell の Architecture}
 \label{sec:shared_memory}
 本研究では、 CPU の他に GPU 上でのプログラミング (GPGPU) にも対応する。
 
@@ -39,6 +39,23 @@
   \caption{CPU Architecture}
   \label{fig:cpuarch}
 \end{figure}
+
+Shared Memory でないプロセッサとして、Cell が挙げられる。
+
+Cell は1基の制御系プロセッサコア PPE ( PowerPC Processer Element ) と
+8基の演算系プロセッサコア SPE ( Synergistic Processer Element ) で構成される。
+各プロセッサコアはEIB (Element Interconnect Bus ) と呼ばれる高速なバスで接続されている。
+また、 EIB はメインメモリや外部入出力デバイスと接続されており、
+各プロセッサコアは EIB を経由してデータアクセスを行う。
+PPE、SPE、メインメモリ、EIB の構成図を図:\ref{fig:cell_arch}に示す。
+\begin{figure}[htpb]
+  \begin{center}
+    \includegraphics[scale=0.8]{./images/cell_arch.pdf}
+  \end{center}
+  \caption{Cell Architecture}
+  \label{fig:cell_arch}
+\end{figure}
+
 \newpage
 %--------
 % OpenCL
@@ -126,3 +143,37 @@
 };
 \end{lstlisting}
 
+\section{Cell Broadband Engine}
+Cell Broadband Engine は、
+ソニー・コンピュータエンタテイメント、ソニー、IBM 、東芝によって開発されたプロセッサである。
+Cell は PPE と SPE によって構成されており、これらは OpenCL や CUDA で言うところの Device にあたる。
+PPE は Cell Broadband Engine のメインプロセッサで、
+複数の SPE をコアプロセッサとして使用できる汎用プロセッサである。
+メインメモリや外部デバイスへの入出力、SPE を制御する役割を担っている。
+
+SPE は PPE によって制御される演算系のプロセッサである。
+\ref{sec:shared_memory}節でも述べた通り、 SPE からメインメモリへ直接アクセスすることはできず、
+ DMA (Direct Memory Access) 転送によってアクセスを行う。
+DMA 転送とは CPU を介さずに周辺装置とメモリとの間でデータ転送を行う事で、
+SPE が持っているコントローラが DMA Controller と通信することで行われる。手順としては以下のようになる。
+
+\begin{enumerate}
+  \item SPE で起動しているプログラムが、コントローラに対して DMA 転送命令を発行
+  \item SPE の持つコントローラが DMA Controller を介して DMA 転送を開始。
+    この間 SPE で起動しているプログラムは停止しない
+  \item 転送が開始したら、SPE プログラムが転送の完了を待つ
+
+\end{enumerate}
+
+Cell の PPE には主に2つの仕様がある。
+
+OpenCL には主に2つの仕様がある。
+
+\begin{itemize}
+\item SPU 拡張 C/C++
+\item libSPE2
+\end{itemize}
+
+SPE 上で動作する、拡張された C/C++ の言語を用いる。
+通常の C/C++ 言語との違いは DMA 転送、SIMD 演算(加算、減算、乗算)に対応していることが挙げられる。
+一方で libSPE2 は PPE が SPE を制御するためのライブラリ群である。
--- a/paper/chapter4.tex	Sat Feb 14 15:50:18 2015 +0900
+++ b/paper/chapter4.tex	Sun Feb 15 11:59:06 2015 +0900
@@ -21,3 +21,7 @@
 しかしマルチコア CPU 上で実行する場合は各 CPU で同じメモリ空間を利用できる。
 よって DMA 転送を用いていた部分をポインタ渡しを行うように修正し、
 メモリに直接アクセスさせることで速度の向上が見込める。
+
+更に、DMA には prefetch 機能がある。
+DMA の転送効率を向上させるため、 DMA で転送する送信データを予め取り込むことができる。
+Cerium では DMA によるprefetch、DMA を用いないポインタ渡し、更に明示的なコピーによるデータ転送をサポートする。
Binary file paper/figures/GPU/.DS_Store has changed
--- a/paper/figures/GPU/fft/bar_plot.sh	Sat Feb 14 15:50:18 2015 +0900
+++ b/paper/figures/GPU/fft/bar_plot.sh	Sun Feb 15 11:59:06 2015 +0900
@@ -9,8 +9,8 @@
 set terminal postscript eps color enhanced
 
 # "sample.eps"として出力
-set output "${fsname}.eps"
-#set output "| epstopdf -f -o=${fsname}.pdf"
+#set output "${fsname}.eps"
+set output "| epstopdf -f -o=${fsname}.pdf"
 
 # x軸名を設定
 set xlabel "Architecture"
--- a/paper/graffle/wordcount.graffle	Sat Feb 14 15:50:18 2015 +0900
+++ b/paper/graffle/wordcount.graffle	Sun Feb 15 11:59:06 2015 +0900
@@ -46,7 +46,7 @@
 	<key>Creator</key>
 	<string>yuhi</string>
 	<key>DisplayScale</key>
-	<string>1 0/72 in = 1 0/72 in</string>
+	<string>1 0/72 in = 1.0000 in</string>
 	<key>GraphDocumentVersion</key>
 	<integer>8</integer>
 	<key>GraphicsList</key>
@@ -349,7 +349,7 @@
 				<key>Pad</key>
 				<integer>0</integer>
 				<key>Text</key>
-				<string>{\rtf1\ansi\ansicpg1252\cocoartf1343\cocoasubrtf160
+				<string>{\rtf1\ansi\ansicpg1252\cocoartf1344\cocoasubrtf720
 \cocoascreenfonts1{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
 {\colortbl;\red255\green255\blue255;}
 \pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc
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 			<key>Text</key>
 			<dict>
 				<key>Text</key>
-				<string>{\rtf1\ansi\ansicpg1252\cocoartf1343\cocoasubrtf160
+				<string>{\rtf1\ansi\ansicpg1252\cocoartf1344\cocoasubrtf720
 \cocoascreenfonts1{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
 {\colortbl;\red255\green255\blue255;}
 \pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc
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 				<integer>0</integer>
 				<key>Text</key>
-				<string>{\rtf1\ansi\ansicpg1252\cocoartf1343\cocoasubrtf160
+				<string>{\rtf1\ansi\ansicpg1252\cocoartf1344\cocoasubrtf720
 \cocoascreenfonts1{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
 {\colortbl;\red255\green255\blue255;}
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@@ -455,7 +455,7 @@
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 			<dict>
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@@ -464,158 +464,6 @@
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-					<true/>
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-			<key>Style</key>
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-				<key>stroke</key>
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-					<key>HeadArrow</key>
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-					<key>Legacy</key>
-					<true/>
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 				<string>{457.35714285714289, 165.78571428571419}</string>
 			</array>
 			<key>Style</key>
@@ -645,11 +493,9 @@
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 				<key>ID</key>
 				<integer>73</integer>
-				<key>Info</key>
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 			</dict>
 			<key>ID</key>
-			<integer>81</integer>
+			<integer>85</integer>
 			<key>Points</key>
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 				<string>{373, 157.49999999999994}</string>
@@ -986,7 +832,7 @@
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 				<integer>0</integer>
 				<key>Text</key>
-				<string>{\rtf1\ansi\ansicpg1252\cocoartf1343\cocoasubrtf160
+				<string>{\rtf1\ansi\ansicpg1252\cocoartf1344\cocoasubrtf720
 \cocoascreenfonts1{\fonttbl\f0\fswiss\fcharset0 Helvetica;}
 {\colortbl;\red255\green255\blue255;}
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+\contentsline {figure}{\numberline {8.4}{\ignorespaces Word Count によるデータ並列実行のベンチマーク}}{29}
+\contentsline {figure}{\numberline {8.5}{\ignorespaces マルチコア CPU、OpenCL、CUDA における FFT}}{30}
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-\contentsline {figure}{\numberline {9.3}{\ignorespaces StarPUにおけるデータ分割}}{32}
+\contentsline {figure}{\numberline {9.1}{\ignorespaces WorkItem ID}}{33}
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--- a/paper/master_paper.toc	Sat Feb 14 15:50:18 2015 +0900
+++ b/paper/master_paper.toc	Sun Feb 15 11:59:06 2015 +0900
@@ -1,40 +1,41 @@
 \contentsline {chapter}{\numberline {第1章}マルチプラットフォームなフレームワークにおける並列プログラミング}{1}
 \contentsline {chapter}{\numberline {第2章}既存のマルチプラットフォームフレームワーク}{3}
-\contentsline {section}{\numberline {2.1}GPU の Architecture}{3}
+\contentsline {section}{\numberline {2.1}GPU/Cell の Architecture}{3}
 \contentsline {section}{\numberline {2.2}OpenCL}{5}
-\contentsline {section}{\numberline {2.3}CUDA}{5}
+\contentsline {section}{\numberline {2.3}CUDA}{6}
 \contentsline {section}{\numberline {2.4}StarPU}{6}
-\contentsline {chapter}{\numberline {第3章}並列プログラミングフレームワーク Cerium}{7}
-\contentsline {section}{\numberline {3.1}Cerium の概要}{7}
-\contentsline {section}{\numberline {3.2}Cerium TaskManager}{7}
-\contentsline {section}{\numberline {3.3}Cerium における Task}{9}
-\contentsline {section}{\numberline {3.4}Task の Scheduling}{10}
-\contentsline {chapter}{\numberline {第4章}Ceriumを用いた例題}{11}
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-\contentsline {section}{\numberline {4.2}Word Count}{13}
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-\contentsline {chapter}{\numberline {第5章}マルチコアへの対応}{16}
-\contentsline {section}{\numberline {5.1}マルチコア上での実行の機構}{16}
-\contentsline {section}{\numberline {5.2}DMA}{16}
-\contentsline {chapter}{\numberline {第6章}GPGPU への対応}{17}
-\contentsline {section}{\numberline {6.1}OpenCL および CUDA による実装}{17}
-\contentsline {section}{\numberline {6.2}データ並列}{18}
-\contentsline {chapter}{\numberline {第7章}並列処理向けI/O}{21}
-\contentsline {section}{\numberline {7.1}mmap}{21}
-\contentsline {section}{\numberline {7.2}Blocked Read による I/O の並列化}{22}
-\contentsline {section}{\numberline {7.3}I/O 専用 Thread の実装}{24}
-\contentsline {chapter}{\numberline {第8章}ベンチマーク}{25}
-\contentsline {section}{\numberline {8.1}実験環境}{25}
-\contentsline {section}{\numberline {8.2}マルチコア}{26}
-\contentsline {section}{\numberline {8.3}GPGPU}{27}
-\contentsline {section}{\numberline {8.4}並列 I/O}{28}
-\contentsline {chapter}{\numberline {第9章}既存のプログラミングフレームワークとの比較}{29}
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-\contentsline {section}{\numberline {9.2}CUDA}{30}
-\contentsline {section}{\numberline {9.3}StarPU}{31}
-\contentsline {chapter}{\numberline {第10章}結論}{33}
-\contentsline {section}{\numberline {10.1}まとめ}{33}
-\contentsline {section}{\numberline {10.2}今後の課題}{33}
-\contentsline {chapter}{謝辞}{34}
-\contentsline {chapter}{参考文献}{35}
-\contentsline {chapter}{発表文献}{36}
+\contentsline {section}{\numberline {2.5}Cell Broadband Engine}{7}
+\contentsline {chapter}{\numberline {第3章}並列プログラミングフレームワーク Cerium}{8}
+\contentsline {section}{\numberline {3.1}Cerium の概要}{8}
+\contentsline {section}{\numberline {3.2}Cerium TaskManager}{8}
+\contentsline {section}{\numberline {3.3}Cerium における Task}{10}
+\contentsline {section}{\numberline {3.4}Task の Scheduling}{11}
+\contentsline {chapter}{\numberline {第4章}Ceriumを用いた例題}{12}
+\contentsline {section}{\numberline {4.1}Bitonic Sort}{12}
+\contentsline {section}{\numberline {4.2}Word Count}{14}
+\contentsline {section}{\numberline {4.3}FFT}{16}
+\contentsline {chapter}{\numberline {第5章}マルチコアへの対応}{17}
+\contentsline {section}{\numberline {5.1}マルチコア上での実行の機構}{17}
+\contentsline {section}{\numberline {5.2}DMA}{17}
+\contentsline {chapter}{\numberline {第6章}GPGPU への対応}{18}
+\contentsline {section}{\numberline {6.1}OpenCL および CUDA による実装}{18}
+\contentsline {section}{\numberline {6.2}データ並列}{19}
+\contentsline {chapter}{\numberline {第7章}並列処理向けI/O}{22}
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+\contentsline {section}{\numberline {8.4}並列 I/O}{31}
+\contentsline {chapter}{\numberline {第9章}既存のプログラミングフレームワークとの比較}{32}
+\contentsline {section}{\numberline {9.1}OpenCL}{32}
+\contentsline {section}{\numberline {9.2}CUDA}{33}
+\contentsline {section}{\numberline {9.3}StarPU}{34}
+\contentsline {chapter}{\numberline {第10章}結論}{36}
+\contentsline {section}{\numberline {10.1}まとめ}{36}
+\contentsline {section}{\numberline {10.2}今後の課題}{36}
+\contentsline {chapter}{謝辞}{37}
+\contentsline {chapter}{参考文献}{38}
+\contentsline {chapter}{発表文献}{39}