Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/mn10300/mn10300.md @ 111:04ced10e8804
gcc 7
author | kono |
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date | Fri, 27 Oct 2017 22:46:09 +0900 |
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children | 84e7813d76e9 |
rev | line source |
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0 | 1 ;; GCC machine description for Matsushita MN10300 |
111 | 2 ;; Copyright (C) 1996-2017 Free Software Foundation, Inc. |
0 | 3 ;; Contributed by Jeff Law (law@cygnus.com). |
4 | |
5 ;; This file is part of GCC. | |
6 | |
7 ;; GCC is free software; you can redistribute it and/or modify | |
8 ;; it under the terms of the GNU General Public License as published by | |
9 ;; the Free Software Foundation; either version 3, or (at your option) | |
10 ;; any later version. | |
11 | |
12 ;; GCC is distributed in the hope that it will be useful, | |
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 ;; GNU General Public License for more details. | |
16 | |
17 ;; You should have received a copy of the GNU General Public License | |
18 ;; along with GCC; see the file COPYING3. If not see | |
19 ;; <http://www.gnu.org/licenses/>. | |
20 | |
21 ;; The original PO technology requires these to be ordered by speed, | |
22 ;; so that assigner will pick the fastest. | |
23 | |
24 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
25 | |
67
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26 (define_constants [ |
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27 (PIC_REG 6) |
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28 (SP_REG 9) |
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29 (MDR_REG 50) |
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30 (CC_REG 51) |
0 | 31 |
32 (UNSPEC_PIC 1) | |
33 (UNSPEC_GOT 2) | |
34 (UNSPEC_GOTOFF 3) | |
35 (UNSPEC_PLT 4) | |
36 (UNSPEC_GOTSYM_OFF 5) | |
67
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37 |
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38 (UNSPEC_EXT 6) |
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39 (UNSPEC_BSCH 7) |
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40 |
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41 ;; This is used to encode LIW patterns. |
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42 (UNSPEC_LIW 8) |
111 | 43 ;; This is for the low overhead loop instructions. |
44 (UNSPEC_SETLB 9) | |
0 | 45 ]) |
46 | |
47 (include "predicates.md") | |
48 (include "constraints.md") | |
67
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49 |
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50 ;; Processor type. This attribute must exactly match the processor_type |
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51 ;; enumeration in mn10300.h. |
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52 (define_attr "cpu" "mn10300,am33,am33_2,am34" |
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53 (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu"))) |
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54 |
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55 ;; Used to control the "enabled" attribute on a per-instruction basis. |
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56 (define_attr "isa" "base,am33,am33_2,am34" |
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57 (const_string "base")) |
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58 |
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59 (define_attr "enabled" "" |
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60 (cond [(eq_attr "isa" "base") |
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61 (const_int 1) |
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62 |
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63 (and (eq_attr "isa" "am33") |
111 | 64 (match_test "TARGET_AM33")) |
67
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65 (const_int 1) |
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66 |
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67 (and (eq_attr "isa" "am33_2") |
111 | 68 (match_test "TARGET_AM33_2")) |
67
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69 (const_int 1) |
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70 |
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71 (and (eq_attr "isa" "am34") |
111 | 72 (match_test "TARGET_AM34")) |
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73 (const_int 1) |
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74 ] |
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75 (const_int 0)) |
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76 ) |
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77 |
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78 (define_mode_iterator INT [QI HI SI]) |
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79 |
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80 |
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81 ;; Bundling of smaller insns into a long instruction word (LIW) |
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82 (define_automaton "liw_bundling") |
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83 (automata_option "ndfa") |
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84 |
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85 (define_cpu_unit "liw_op1_u,liw_op2_u" "liw_bundling") |
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86 |
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87 (define_attr "liw" "op1,op2,both,either" |
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88 (const_string "both")) |
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89 ;; Note: this list must match the one defined for liw_op_names[]. |
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90 (define_attr "liw_op" "add,cmp,sub,mov,and,or,xor,asr,lsr,asl,none,max" |
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91 (const_string "none")) |
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92 |
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93 (define_insn_reservation "liw_op1" 1 |
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94 (and (ior (eq_attr "cpu" "am33") |
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95 (eq_attr "cpu" "am33_2") |
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96 (eq_attr "cpu" "am34")) |
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97 (eq_attr "liw" "op1")) |
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98 "liw_op1_u"); |
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99 (define_insn_reservation "liw_op2" 1 |
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100 (and (ior (eq_attr "cpu" "am33") |
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101 (eq_attr "cpu" "am33_2") |
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102 (eq_attr "cpu" "am34")) |
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103 (eq_attr "liw" "op2")) |
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104 "liw_op2_u"); |
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105 (define_insn_reservation "liw_both" 1 |
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106 (and (ior (eq_attr "cpu" "am33") |
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107 (eq_attr "cpu" "am33_2") |
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108 (eq_attr "cpu" "am34")) |
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109 (eq_attr "liw" "both")) |
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110 "liw_op1_u + liw_op2_u"); |
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111 (define_insn_reservation "liw_either" 1 |
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112 (and (ior (eq_attr "cpu" "am33") |
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113 (eq_attr "cpu" "am33_2") |
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114 (eq_attr "cpu" "am34")) |
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115 (eq_attr "liw" "either")) |
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116 "liw_op1_u | liw_op2_u"); |
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117 |
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118 ;; ---------------------------------------------------------------------- |
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119 ;; Pipeline description. |
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120 ;; ---------------------------------------------------------------------- |
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121 |
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122 ;; The AM33 only has a single pipeline. It has five stages (fetch, |
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123 ;; decode, execute, memory access, writeback) each of which normally |
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124 ;; takes a single CPU clock cycle. |
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125 |
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126 ;; The timings attribute consists of two numbers, the first is the |
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127 ;; throughput, which is the number of cycles the instruction takes |
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128 ;; to execute and generate a result. The second is the latency |
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129 ;; which is the effective number of cycles the instruction takes to |
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130 ;; execute if its result is used by the following instruction. The |
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131 ;; latency is always greater than or equal to the throughput. |
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132 ;; These values were taken from the Appendix of the "MN103E Series |
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133 ;; Instruction Manual" and the timings for the AM34. |
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134 |
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135 ;; Note - it would be nice to use strings rather than integers for |
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136 ;; the possible values of this attribute, so that we can have the |
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137 ;; gcc build mechanism check for values that are not supported by |
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138 ;; the reservations below. But this will not work because the code |
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139 ;; in mn10300_adjust_sched_cost() needs integers not strings. |
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140 |
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141 (define_attr "timings" "" (const_int 11)) |
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142 |
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143 (define_automaton "pipelining") |
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144 (define_cpu_unit "throughput" "pipelining") |
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145 |
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146 (define_insn_reservation "throughput__1_latency__1" 1 |
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147 (eq_attr "timings" "11") "throughput") |
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148 (define_insn_reservation "throughput__1_latency__2" 2 |
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149 (eq_attr "timings" "12") "throughput,nothing") |
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150 (define_insn_reservation "throughput__1_latency__3" 3 |
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151 (eq_attr "timings" "13") "throughput,nothing*2") |
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152 (define_insn_reservation "throughput__1_latency__4" 4 |
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153 (eq_attr "timings" "14") "throughput,nothing*3") |
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154 (define_insn_reservation "throughput__2_latency__2" 2 |
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155 (eq_attr "timings" "22") "throughput*2") |
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156 (define_insn_reservation "throughput__2_latency__3" 3 |
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157 (eq_attr "timings" "23") "throughput*2,nothing") |
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158 (define_insn_reservation "throughput__2_latency__4" 4 |
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159 (eq_attr "timings" "24") "throughput*2,nothing*2") |
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160 (define_insn_reservation "throughput__2_latency__5" 5 |
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161 (eq_attr "timings" "25") "throughput*2,nothing*3") |
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162 (define_insn_reservation "throughput__3_latency__3" 3 |
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163 (eq_attr "timings" "33") "throughput*3") |
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164 (define_insn_reservation "throughput__3_latency__7" 7 |
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165 (eq_attr "timings" "37") "throughput*3,nothing*4") |
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166 (define_insn_reservation "throughput__4_latency__4" 4 |
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167 (eq_attr "timings" "44") "throughput*4") |
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168 (define_insn_reservation "throughput__4_latency__7" 7 |
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169 (eq_attr "timings" "47") "throughput*4,nothing*3") |
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170 (define_insn_reservation "throughput__4_latency__8" 8 |
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171 (eq_attr "timings" "48") "throughput*4,nothing*4") |
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172 (define_insn_reservation "throughput__5_latency__5" 5 |
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173 (eq_attr "timings" "55") "throughput*5") |
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174 (define_insn_reservation "throughput__6_latency__6" 6 |
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175 (eq_attr "timings" "66") "throughput*6") |
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176 (define_insn_reservation "throughput__7_latency__7" 7 |
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177 (eq_attr "timings" "77") "throughput*7") |
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178 (define_insn_reservation "throughput__7_latency__8" 8 |
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179 (eq_attr "timings" "78") "throughput*7,nothing") |
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180 (define_insn_reservation "throughput__8_latency__8" 8 |
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181 (eq_attr "timings" "88") "throughput*8") |
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182 (define_insn_reservation "throughput__9_latency__9" 9 |
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183 (eq_attr "timings" "99") "throughput*9") |
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184 (define_insn_reservation "throughput__8_latency_14" 14 |
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185 (eq_attr "timings" "814") "throughput*8,nothing*6") |
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186 (define_insn_reservation "throughput__9_latency_10" 10 |
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187 (eq_attr "timings" "910") "throughput*9,nothing") |
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188 (define_insn_reservation "throughput_10_latency_10" 10 |
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189 (eq_attr "timings" "1010") "throughput*10") |
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190 (define_insn_reservation "throughput_12_latency_16" 16 |
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191 (eq_attr "timings" "1216") "throughput*12,nothing*4") |
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192 (define_insn_reservation "throughput_13_latency_13" 13 |
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193 (eq_attr "timings" "1313") "throughput*13") |
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194 (define_insn_reservation "throughput_14_latency_14" 14 |
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195 (eq_attr "timings" "1414") "throughput*14") |
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196 (define_insn_reservation "throughput_13_latency_17" 17 |
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197 (eq_attr "timings" "1317") "throughput*13,nothing*4") |
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198 (define_insn_reservation "throughput_23_latency_27" 27 |
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199 (eq_attr "timings" "2327") "throughput*23,nothing*4") |
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200 (define_insn_reservation "throughput_25_latency_31" 31 |
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201 (eq_attr "timings" "2531") "throughput*25,nothing*6") |
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202 (define_insn_reservation "throughput_38_latency_39" 39 |
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203 (eq_attr "timings" "3839") "throughput*38,nothing") |
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204 (define_insn_reservation "throughput_39_latency_40" 40 |
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205 (eq_attr "timings" "3940") "throughput*39,nothing") |
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206 (define_insn_reservation "throughput_40_latency_40" 40 |
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207 (eq_attr "timings" "4040") "throughput*40") |
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208 (define_insn_reservation "throughput_41_latency_42" 42 |
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209 (eq_attr "timings" "4142") "throughput*41,nothing") |
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210 (define_insn_reservation "throughput_42_latency_43" 44 |
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211 (eq_attr "timings" "4243") "throughput*42,nothing") |
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212 (define_insn_reservation "throughput_43_latency_44" 44 |
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213 (eq_attr "timings" "4344") "throughput*43,nothing") |
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214 (define_insn_reservation "throughput_45_latency_46" 46 |
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215 (eq_attr "timings" "4546") "throughput*45,nothing") |
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216 (define_insn_reservation "throughput_47_latency_53" 53 |
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217 (eq_attr "timings" "4753") "throughput*47,nothing*6") |
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218 |
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219 ;; Note - the conflict between memory load/store instructions |
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220 ;; and floating point instructions described in section 1-7-4 |
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221 ;; of Chapter 3 of the MN103E Series Instruction Manual is |
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222 ;; handled by the mn10300_adjust_sched_cost function. |
0 | 223 |
224 ;; ---------------------------------------------------------------------- | |
225 ;; MOVE INSTRUCTIONS | |
226 ;; ---------------------------------------------------------------------- | |
227 | |
228 ;; movqi | |
229 | |
230 (define_expand "movqi" | |
67
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231 [(set (match_operand:QI 0 "nonimmediate_operand") |
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232 (match_operand:QI 1 "general_operand"))] |
0 | 233 "" |
234 { | |
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235 /* One of the ops has to be in a register. */ |
0 | 236 if (!register_operand (operand0, QImode) |
237 && !register_operand (operand1, QImode)) | |
67
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238 operands[1] = force_reg (QImode, operand1); |
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239 }) |
0 | 240 |
67
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241 (define_insn "*movqi_internal" |
111 | 242 [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d") |
243 (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D,d,*z"))] | |
67
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244 "(register_operand (operands[0], QImode) |
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245 || register_operand (operands[1], QImode))" |
0 | 246 { |
247 switch (which_alternative) | |
248 { | |
249 case 0: | |
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250 return ""; |
0 | 251 case 1: |
252 case 2: | |
111 | 253 case 5: |
254 case 6: | |
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255 return "mov %1,%0"; |
0 | 256 case 3: |
257 case 4: | |
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258 return "movbu %1,%0"; |
0 | 259 default: |
260 gcc_unreachable (); | |
261 } | |
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262 } |
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263 [(set_attr_alternative "timings" |
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264 [(const_int 11) |
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265 (const_int 11) |
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266 (const_int 11) |
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267 (if_then_else (eq_attr "cpu" "am34") |
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268 (const_int 13) (const_int 24)) |
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269 (if_then_else (eq_attr "cpu" "am34") |
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270 (const_int 11) (const_int 22)) |
111 | 271 (const_int 11) |
272 (const_int 11) | |
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273 ])] |
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274 ) |
0 | 275 |
276 ;; movhi | |
277 | |
278 (define_expand "movhi" | |
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279 [(set (match_operand:HI 0 "nonimmediate_operand") |
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280 (match_operand:HI 1 "general_operand"))] |
0 | 281 "" |
282 { | |
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283 /* One of the ops has to be in a register. */ |
0 | 284 if (!register_operand (operand1, HImode) |
285 && !register_operand (operand0, HImode)) | |
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286 operands[1] = force_reg (HImode, operand1); |
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287 }) |
0 | 288 |
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289 (define_insn "*movhi_internal" |
111 | 290 [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d") |
291 (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D,d,*z"))] | |
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292 "(register_operand (operands[0], HImode) |
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293 || register_operand (operands[1], HImode))" |
0 | 294 { |
295 switch (which_alternative) | |
296 { | |
297 case 0: | |
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298 return ""; |
0 | 299 case 1: |
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300 /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes. |
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301 We have "MOV imm16,Dn" at 3 bytes. The only win for the 4 byte |
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302 movu is for an 8-bit unsigned move into Rn. */ |
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303 if (TARGET_AM33 |
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304 && CONST_INT_P (operands[1]) |
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305 && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff) |
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306 && REGNO_EXTENDED_P (REGNO (operands[0]), 1)) |
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307 return "movu %1,%0"; |
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308 /* FALLTHRU */ |
111 | 309 case 5: |
310 case 6: | |
0 | 311 case 2: |
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312 return "mov %1,%0"; |
0 | 313 case 3: |
314 case 4: | |
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315 return "movhu %1,%0"; |
0 | 316 default: |
317 gcc_unreachable (); | |
318 } | |
67
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319 } |
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320 [(set_attr_alternative "timings" |
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321 [(const_int 11) |
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322 (const_int 11) |
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323 (if_then_else (eq_attr "cpu" "am34") |
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324 (const_int 11) (const_int 22)) |
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325 (if_then_else (eq_attr "cpu" "am34") |
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326 (const_int 13) (const_int 24)) |
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327 (if_then_else (eq_attr "cpu" "am34") |
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328 (const_int 11) (const_int 22)) |
111 | 329 (if_then_else (eq_attr "cpu" "am34") |
330 (const_int 11) (const_int 22)) | |
331 (if_then_else (eq_attr "cpu" "am34") | |
332 (const_int 11) (const_int 22)) | |
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333 ])] |
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334 ) |
0 | 335 |
336 ;; movsi and helpers | |
337 | |
338 ;; We use this to handle addition of two values when one operand is the | |
339 ;; stack pointer and the other is a memory reference of some kind. Reload | |
340 ;; does not handle them correctly without this expander. | |
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341 (define_expand "reload_plus_sp_const" |
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342 [(set (match_operand:SI 0 "register_operand" "=r") |
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343 (match_operand:SI 1 "impossible_plus_operand" "")) |
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344 (clobber (match_operand:SI 2 "register_operand" "=&A"))] |
0 | 345 "" |
346 { | |
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347 rtx dest, scratch, other; |
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348 |
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349 dest = operands[0]; |
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350 scratch = operands[2]; |
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351 |
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352 other = XEXP (operands[1], 1); |
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353 if (other == stack_pointer_rtx) |
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354 other = XEXP (operands[1], 0); |
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355 |
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356 if (true_regnum (other) == true_regnum (dest)) |
0 | 357 { |
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358 gcc_assert (true_regnum (scratch) != true_regnum (dest)); |
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359 emit_move_insn (scratch, stack_pointer_rtx); |
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360 emit_insn (gen_addsi3 (dest, dest, scratch)); |
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361 } |
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362 else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS) |
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363 { |
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364 emit_move_insn (dest, stack_pointer_rtx); |
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365 if (other == stack_pointer_rtx) |
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366 emit_insn (gen_addsi3 (dest, dest, dest)); |
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367 else if (other != const0_rtx) |
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368 emit_insn (gen_addsi3 (dest, dest, other)); |
0 | 369 } |
370 else | |
371 { | |
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372 emit_move_insn (scratch, stack_pointer_rtx); |
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373 if (other == stack_pointer_rtx) |
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374 { |
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375 emit_move_insn (dest, scratch); |
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376 emit_insn (gen_addsi3 (dest, dest, dest)); |
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377 } |
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378 else if (other != const0_rtx) |
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379 { |
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380 emit_move_insn (dest, other); |
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381 emit_insn (gen_addsi3 (dest, dest, scratch)); |
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382 } |
0 | 383 else |
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384 emit_move_insn (dest, scratch); |
0 | 385 } |
386 DONE; | |
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387 }) |
0 | 388 |
389 (define_expand "movsi" | |
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390 [(set (match_operand:SI 0 "nonimmediate_operand") |
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391 (match_operand:SI 1 "general_operand"))] |
0 | 392 "" |
393 { | |
67
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394 /* One of the ops has to be in a register. */ |
0 | 395 if (!register_operand (operand1, SImode) |
396 && !register_operand (operand0, SImode)) | |
67
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397 operands[1] = force_reg (SImode, operand1); |
0 | 398 if (flag_pic) |
399 { | |
400 rtx temp; | |
401 if (SYMBOLIC_CONST_P (operands[1])) | |
402 { | |
67
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403 if (MEM_P (operands[0])) |
0 | 404 operands[1] = force_reg (Pmode, operands[1]); |
405 else | |
406 { | |
407 temp = (!can_create_pseudo_p () | |
408 ? operands[0] | |
409 : gen_reg_rtx (Pmode)); | |
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410 operands[1] = mn10300_legitimize_pic_address (operands[1], temp); |
0 | 411 } |
412 } | |
413 else if (GET_CODE (operands[1]) == CONST | |
414 && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
415 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0))) | |
416 { | |
417 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); | |
67
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418 temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0), |
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419 temp); |
0 | 420 operands[1] = expand_binop (SImode, add_optab, temp, |
421 XEXP (XEXP (operands[1], 0), 1), | |
422 (!can_create_pseudo_p () | |
423 ? temp | |
424 : gen_reg_rtx (Pmode)), | |
425 0, OPTAB_LIB_WIDEN); | |
426 } | |
427 } | |
67
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428 }) |
0 | 429 |
67
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430 (define_insn "*movsi_internal" |
0 | 431 [(set (match_operand:SI 0 "nonimmediate_operand" |
67
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432 "=r,r,r,r,m,r, A,*y,*y,*z,*d") |
0 | 433 (match_operand:SI 1 "general_operand" |
67
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434 " 0,O,i,r,r,m,*y, A, i,*d,*z"))] |
0 | 435 "register_operand (operands[0], SImode) |
436 || register_operand (operands[1], SImode)" | |
437 { | |
438 switch (which_alternative) | |
439 { | |
440 case 0: | |
67
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441 return ""; |
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442 case 1: /* imm-reg. */ |
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443 case 2: |
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444 /* See movhi for a discussion of sizes for 8-bit movu. Note that the |
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445 24-bit movu is 6 bytes, which is the same size as the full 32-bit |
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446 mov form for An and Dn. So again movu is only a win for Rn. */ |
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447 if (TARGET_AM33 |
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448 && CONST_INT_P (operands[1]) |
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449 && REGNO_EXTENDED_P (REGNO (operands[0]), 1)) |
0 | 450 { |
451 HOST_WIDE_INT val = INTVAL (operands[1]); | |
67
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452 if (IN_RANGE (val, 0x80, 0xff) |
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453 || IN_RANGE (val, 0x800000, 0xffffff)) |
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454 return "movu %1,%0"; |
0 | 455 } |
67
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456 /* FALLTHRU */ |
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457 case 3: /* reg-reg */ |
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458 case 4: /* reg-mem */ |
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459 case 5: /* mem-reg */ |
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460 case 6: /* sp-reg */ |
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461 case 7: /* reg-sp */ |
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462 case 8: /* imm-sp */ |
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463 case 9: /* reg-mdr */ |
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464 case 10: /* mdr-reg */ |
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465 return "mov %1,%0"; |
0 | 466 default: |
467 gcc_unreachable (); | |
468 } | |
67
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469 } |
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470 [(set_attr "isa" "*,*,*,*,*,*,*,*,am33,*,*") |
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471 (set_attr "liw" "*,either,*,either,*,*,*,*,*,*,*") |
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472 (set_attr "liw_op" "mov") |
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473 (set_attr_alternative "timings" |
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474 [(const_int 11) |
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475 (const_int 22) |
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476 (const_int 22) |
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477 (const_int 11) |
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478 (if_then_else (eq_attr "cpu" "am34") |
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479 (const_int 11) (const_int 22)) |
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480 (if_then_else (eq_attr "cpu" "am34") |
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481 (const_int 13) (const_int 24)) |
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482 (if_then_else (eq_attr "cpu" "am34") |
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483 (const_int 11) (const_int 22)) |
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484 (if_then_else (eq_attr "cpu" "am34") |
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485 (const_int 13) (const_int 24)) |
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486 (const_int 11) |
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487 (const_int 11) |
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488 (const_int 11) |
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489 ])] |
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490 ) |
0 | 491 |
67
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492 (define_expand "movsf" |
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493 [(set (match_operand:SF 0 "nonimmediate_operand") |
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494 (match_operand:SF 1 "general_operand"))] |
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495 "TARGET_AM33_2" |
0 | 496 { |
67
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497 /* One of the ops has to be in a register. */ |
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498 if (!register_operand (operand1, SFmode) |
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499 && !register_operand (operand0, SFmode)) |
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500 operands[1] = force_reg (SFmode, operand1); |
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501 }) |
0 | 502 |
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503 (define_insn "*movsf_internal" |
111 | 504 [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q,z,d") |
505 (match_operand:SF 1 "general_operand" " 0,F,F,r,f,f,r,m,r,Q,f,d,z"))] | |
67
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506 "TARGET_AM33_2 |
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507 && (register_operand (operands[0], SFmode) |
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508 || register_operand (operands[1], SFmode))" |
0 | 509 { |
510 switch (which_alternative) | |
511 { | |
67
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512 case 0: |
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513 return ""; |
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514 case 1: |
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515 case 3: |
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516 case 7: |
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517 case 8: |
111 | 518 case 11: |
519 case 12: | |
67
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520 return "mov %1,%0"; |
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521 case 2: |
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522 case 4: |
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523 case 5: |
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524 case 6: |
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525 case 9: |
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526 case 10: |
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527 return "fmov %1,%0"; |
0 | 528 default: |
529 gcc_unreachable (); | |
530 } | |
67
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531 } |
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532 [(set_attr_alternative "timings" |
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533 [(const_int 11) |
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534 (const_int 22) |
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535 (if_then_else (eq_attr "cpu" "am34") |
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536 (const_int 47) (const_int 25)) |
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537 (const_int 11) |
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538 (if_then_else (eq_attr "cpu" "am34") |
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539 (const_int 13) (const_int 14)) |
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540 (if_then_else (eq_attr "cpu" "am34") |
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541 (const_int 13) (const_int 12)) |
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542 (if_then_else (eq_attr "cpu" "am34") |
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543 (const_int 13) (const_int 14)) |
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544 (if_then_else (eq_attr "cpu" "am34") |
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545 (const_int 13) (const_int 24)) |
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546 (if_then_else (eq_attr "cpu" "am34") |
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547 (const_int 13) (const_int 24)) |
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548 (if_then_else (eq_attr "cpu" "am34") |
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549 (const_int 13) (const_int 24)) |
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550 (if_then_else (eq_attr "cpu" "am34") |
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551 (const_int 13) (const_int 24)) |
111 | 552 (const_int 22) |
553 (const_int 22) | |
67
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554 ])] |
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555 ) |
0 | 556 |
67
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557 ;; If the flags register is not live, generate CLR instead of MOV 0. |
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558 ;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal |
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559 ;; but not a win for ADDRESS_REGS. |
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560 (define_peephole2 |
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561 [(set (match_operand:INT 0 "register_operand" "") (const_int 0))] |
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562 "peep2_regno_dead_p (0, CC_REG) |
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563 && (REGNO_DATA_P (REGNO (operands[0]), 1) |
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564 || REGNO_EXTENDED_P (REGNO (operands[0]), 1))" |
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565 [(parallel [(set (match_dup 0) (const_int 0)) |
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566 (clobber (reg:CC CC_REG))])] |
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567 ) |
0 | 568 |
67
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569 (define_insn "*mov<mode>_clr" |
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570 [(set (match_operand:INT 0 "register_operand" "=D") |
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571 (const_int 0)) |
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572 (clobber (reg:CC CC_REG))] |
0 | 573 "" |
67
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574 "clr %0" |
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575 ) |
0 | 576 |
577 ;; ---------------------------------------------------------------------- | |
578 ;; ADD INSTRUCTIONS | |
579 ;; ---------------------------------------------------------------------- | |
580 | |
67
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581 (define_insn "addsi3" |
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582 [(set (match_operand:SI 0 "register_operand" "=r,r,r,!*y,!r") |
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583 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0, r") |
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584 (match_operand:SI 2 "nonmemory_operand" "r,O,i, i, r"))) |
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585 (clobber (reg:CC CC_REG))] |
0 | 586 "" |
67
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587 { return mn10300_output_add (operands, false); } |
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588 [(set_attr "timings" "11,11,11,11,22") |
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589 (set_attr "liw" "either,either,*,*,*") |
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590 (set_attr "liw_op" "add")] |
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591 ) |
0 | 592 |
67
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593 ;; Note that ADD IMM,SP does not set the flags, so omit that here. |
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594 (define_insn "*addsi3_flags" |
111 | 595 [(set (reg CC_REG) |
596 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0, r") | |
597 (match_operand:SI 2 "nonmemory_operand" "ri, r")) | |
598 (const_int 0))) | |
599 (set (match_operand:SI 0 "register_operand" "=r,!r") | |
600 (plus:SI (match_dup 1) (match_dup 2)))] | |
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601 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)" |
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602 { return mn10300_output_add (operands, true); } |
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603 [(set_attr "timings" "11,22")] |
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604 ) |
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605 |
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606 ;; A helper to expand the above, with the CC_MODE filled in. |
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607 (define_expand "addsi3_flags" |
111 | 608 [(parallel [(set (reg:CCZNC CC_REG) |
609 (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2)) | |
610 (const_int 0))) | |
611 (set (match_operand:SI 0 "register_operand") | |
67
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612 (plus:SI (match_operand:SI 1 "register_operand") |
111 | 613 (match_operand:SI 2 "nonmemory_operand")))])] |
67
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614 "" |
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615 ) |
0 | 616 |
67
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617 (define_insn "addc_internal" |
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618 [(set (match_operand:SI 0 "register_operand" "=D,r,r") |
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619 (plus:SI |
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620 (plus:SI |
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621 (ltu:SI (reg:CC CC_REG) (const_int 0)) |
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622 (match_operand:SI 1 "register_operand" "%0,0,r")) |
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623 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r"))) |
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624 (clobber (reg:CC CC_REG))] |
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625 "reload_completed" |
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626 "@ |
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627 addc %2,%0 |
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628 addc %2,%0 |
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629 addc %2,%1,%0" |
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630 [(set_attr "isa" "*,am33,am33")] |
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631 ) |
0 | 632 |
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633 (define_expand "adddi3" |
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634 [(set (match_operand:DI 0 "register_operand" "") |
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635 (plus:DI (match_operand:DI 1 "register_operand" "") |
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636 (match_operand:DI 2 "nonmemory_operand" "")))] |
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637 "" |
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638 { |
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639 rtx op0l, op0h, op1l, op1h, op2l, op2h; |
0 | 640 |
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641 op0l = gen_lowpart (SImode, operands[0]); |
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642 op1l = gen_lowpart (SImode, operands[1]); |
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643 op2l = gen_lowpart (SImode, operands[2]); |
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644 op0h = gen_highpart (SImode, operands[0]); |
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645 op1h = gen_highpart (SImode, operands[1]); |
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646 op2h = gen_highpart_mode (SImode, DImode, operands[2]); |
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647 |
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648 if (!reg_or_am33_const_operand (op2h, SImode)) |
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649 op2h = force_reg (SImode, op2h); |
0 | 650 |
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651 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h)); |
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652 DONE; |
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653 }) |
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654 |
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655 ;; Note that reload only supports one commutative operand. Thus we cannot |
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656 ;; auto-swap both the high and low outputs with their matching constraints. |
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657 ;; For MN103, we're strapped for registers but thankfully the alternatives |
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658 ;; are few. For AM33, it becomes much easier to not represent the early |
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659 ;; clobber and 6 permutations of immediate and three-operand adds, but |
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660 ;; instead allocate a scratch register and do the expansion by hand. |
0 | 661 |
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662 (define_insn_and_split "adddi3_internal" |
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663 [(set (match_operand:SI 0 "register_operand" "=r, r, r") |
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664 (plus:SI (match_operand:SI 2 "register_operand" "%0, 0, r") |
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665 (match_operand:SI 3 "nonmemory_operand" "ri,ri,ri"))) |
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666 (set (match_operand:SI 1 "register_operand" "=D, D, r") |
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667 (plus:SI |
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668 (plus:SI |
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669 (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2)) |
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670 (match_operand:SI 4 "register_operand" " 1, D, r")) |
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671 (match_operand:SI 5 "reg_or_am33_const_operand" " D, 1,ri"))) |
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672 (clobber (match_scratch:SI 6 "=X, X,&r")) |
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673 (clobber (reg:CC CC_REG))] |
0 | 674 "" |
67
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675 "#" |
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676 "reload_completed" |
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677 [(const_int 0)] |
0 | 678 { |
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679 rtx op0l = operands[0]; |
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680 rtx op0h = operands[1]; |
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681 rtx op1l = operands[2]; |
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682 rtx op2l = operands[3]; |
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683 rtx op1h = operands[4]; |
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684 rtx op2h = operands[5]; |
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685 rtx scratch = operands[6]; |
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686 rtx x; |
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687 |
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688 if (reg_overlap_mentioned_p (op0l, op1h)) |
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689 { |
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690 emit_move_insn (scratch, op0l); |
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691 op1h = scratch; |
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692 if (reg_overlap_mentioned_p (op0l, op2h)) |
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693 op2h = scratch; |
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694 } |
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695 else if (reg_overlap_mentioned_p (op0l, op2h)) |
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696 { |
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697 emit_move_insn (scratch, op0l); |
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698 op2h = scratch; |
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699 } |
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700 |
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701 if (rtx_equal_p (op0l, op1l)) |
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702 ; |
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703 else if (rtx_equal_p (op0l, op2l)) |
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704 x = op1l, op1l = op2l, op2l = x; |
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705 else |
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706 { |
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707 gcc_assert (TARGET_AM33); |
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708 if (!REG_P (op2l)) |
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709 { |
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710 emit_move_insn (op0l, op2l); |
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711 op2l = op1l; |
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712 op1l = op0l; |
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713 } |
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714 } |
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715 emit_insn (gen_addsi3_flags (op0l, op1l, op2l)); |
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716 |
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717 if (rtx_equal_p (op0h, op1h)) |
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718 ; |
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719 else if (rtx_equal_p (op0h, op2h)) |
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720 x = op1h, op1h = op2h, op2h = x; |
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721 else |
0 | 722 { |
67
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723 gcc_assert (TARGET_AM33); |
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724 if (!REG_P (op2h)) |
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725 { |
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726 emit_move_insn (op0h, op2h); |
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727 op2h = op1h; |
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728 op1h = op0h; |
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729 } |
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730 } |
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731 emit_insn (gen_addc_internal (op0h, op1h, op2h)); |
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732 DONE; |
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733 } |
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734 [(set_attr "isa" "*,*,am33")] |
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735 ) |
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736 |
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737 ;; The following pattern is generated by combine when it proves that one |
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738 ;; of the inputs to the low-part of the double-word add is zero, and thus |
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739 ;; no carry is generated into the high-part. |
0 | 740 |
67
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741 (define_insn_and_split "*adddi3_degenerate" |
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742 [(set (match_operand:SI 0 "register_operand" "=&r,&r") |
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743 (match_operand:SI 2 "nonmemory_operand" " 0, 0")) |
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744 (set (match_operand:SI 1 "register_operand" "=r , r") |
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745 (plus:SI (match_operand:SI 3 "register_operand" "%1 , r") |
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746 (match_operand:SI 4 "nonmemory_operand" "ri, r"))) |
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747 (clobber (reg:CC CC_REG))] |
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748 "" |
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749 "#" |
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750 "" |
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751 [(const_int 0)] |
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752 { |
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753 rtx scratch = NULL_RTX; |
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754 if (!rtx_equal_p (operands[0], operands[2])) |
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755 { |
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756 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])); |
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757 if (reg_overlap_mentioned_p (operands[0], operands[3]) |
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758 || reg_overlap_mentioned_p (operands[0], operands[4])) |
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759 { |
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760 scratch = gen_reg_rtx (SImode); |
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761 emit_move_insn (scratch, operands[2]); |
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762 } |
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763 else |
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764 emit_move_insn (operands[0], operands[2]); |
0 | 765 } |
67
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766 emit_insn (gen_addsi3 (operands[1], operands[3], operands[4])); |
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767 if (scratch) |
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768 emit_move_insn (operands[0], scratch); |
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769 DONE; |
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770 }) |
0 | 771 |
772 ;; ---------------------------------------------------------------------- | |
773 ;; SUBTRACT INSTRUCTIONS | |
774 ;; ---------------------------------------------------------------------- | |
775 | |
67
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776 (define_insn "subsi3" |
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777 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") |
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778 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r") |
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779 (match_operand:SI 2 "nonmemory_operand" "r,O,i,r"))) |
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780 (clobber (reg:CC CC_REG))] |
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781 "" |
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782 "@ |
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783 sub %2,%0 |
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784 sub %2,%0 |
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785 sub %2,%0 |
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786 sub %2,%1,%0" |
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787 [(set_attr "isa" "*,*,*,am33") |
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788 (set_attr "liw" "either,either,*,*") |
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789 (set_attr "liw_op" "sub") |
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790 (set_attr "timings" "11,11,11,22")] |
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791 ) |
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792 |
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793 (define_insn "*subsi3_flags" |
111 | 794 [(set (reg CC_REG) |
795 (compare (minus:SI (match_operand:SI 1 "register_operand" "0, r") | |
796 (match_operand:SI 2 "nonmemory_operand" "ri,r")) | |
797 (const_int 0))) | |
798 (set (match_operand:SI 0 "register_operand" "=r, r") | |
799 (minus:SI (match_dup 1) (match_dup 2)))] | |
67
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800 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)" |
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801 "@ |
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802 sub %2,%0 |
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803 sub %2,%1,%0" |
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804 [(set_attr "isa" "*,am33") |
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805 (set_attr "timings" "11,22")] |
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806 ) |
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807 |
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808 ;; A helper to expand the above, with the CC_MODE filled in. |
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809 (define_expand "subsi3_flags" |
111 | 810 [(parallel [(set (reg:CCZNC CC_REG) |
811 (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2)) | |
812 (const_int 0))) | |
813 (set (match_operand:SI 0 "register_operand") | |
67
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814 (minus:SI (match_operand:SI 1 "register_operand") |
111 | 815 (match_operand:SI 2 "nonmemory_operand")))])] |
0 | 816 "" |
67
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817 ) |
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818 |
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819 (define_insn "subc_internal" |
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820 [(set (match_operand:SI 0 "register_operand" "=D,r,r") |
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821 (minus:SI |
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822 (minus:SI (match_operand:SI 1 "register_operand" " 0,0,r") |
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823 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r")) |
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824 (geu:SI (reg:CC CC_REG) (const_int 0)))) |
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825 (clobber (reg:CC CC_REG))] |
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826 "reload_completed" |
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827 "@ |
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828 subc %2,%0 |
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829 subc %2,%0 |
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830 subc %2,%1,%0" |
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831 [(set_attr "isa" "*,am33,am33")] |
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832 ) |
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833 |
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834 (define_expand "subdi3" |
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835 [(set (match_operand:DI 0 "register_operand" "") |
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836 (minus:DI (match_operand:DI 1 "register_operand" "") |
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837 (match_operand:DI 2 "nonmemory_operand" "")))] |
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838 "" |
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839 { |
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840 rtx op0l, op0h, op1l, op1h, op2l, op2h; |
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841 |
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842 op0l = gen_lowpart (SImode, operands[0]); |
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843 op1l = gen_lowpart (SImode, operands[1]); |
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844 op2l = gen_lowpart (SImode, operands[2]); |
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845 op0h = gen_highpart (SImode, operands[0]); |
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846 op1h = gen_highpart (SImode, operands[1]); |
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847 op2h = gen_highpart_mode (SImode, DImode, operands[2]); |
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848 |
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849 if (!reg_or_am33_const_operand (op2h, SImode)) |
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850 op2h = force_reg (SImode, op2h); |
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851 |
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852 emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op1h, op2l, op2h)); |
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853 DONE; |
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854 }) |
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855 |
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856 ;; As with adddi3, the use of the scratch register helps reduce the |
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857 ;; number of permutations for AM33. |
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858 ;; ??? The early clobber on op0 avoids a reload bug wherein both output |
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859 ;; registers are set the same. Consider negate, where both op2 and op3 |
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860 ;; are 0, are csed to the same input register, and reload fails to undo |
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861 ;; the cse when satisfying the matching constraints. |
0 | 862 |
67
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863 (define_insn_and_split "subdi3_internal" |
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864 [(set (match_operand:SI 0 "register_operand" "=&r, r") |
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865 (minus:SI |
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866 (match_operand:SI 2 "register_operand" " 0, r") |
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867 (match_operand:SI 4 "nonmemory_operand" " ri,ri"))) |
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868 (set (match_operand:SI 1 "register_operand" "=D , r") |
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869 (minus:SI |
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870 (minus:SI |
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871 (match_operand:SI 3 "register_operand" " 1, r") |
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872 (match_operand:SI 5 "reg_or_am33_const_operand" " D,ri")) |
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873 (ltu:SI (match_dup 2) (match_dup 4)))) |
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874 (clobber (match_scratch:SI 6 "=X ,&r")) |
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875 (clobber (reg:CC CC_REG))] |
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876 "" |
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877 "#" |
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878 "reload_completed" |
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879 [(const_int 0)] |
0 | 880 { |
67
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881 rtx op0l = operands[0]; |
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882 rtx op0h = operands[1]; |
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883 rtx op1l = operands[2]; |
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884 rtx op1h = operands[3]; |
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885 rtx op2l = operands[4]; |
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886 rtx op2h = operands[5]; |
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887 rtx scratch = operands[6]; |
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888 |
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889 if (reg_overlap_mentioned_p (op0l, op1h)) |
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890 { |
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891 emit_move_insn (scratch, op0l); |
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892 op1h = scratch; |
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893 if (reg_overlap_mentioned_p (op0l, op2h)) |
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894 op2h = scratch; |
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895 } |
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896 else if (reg_overlap_mentioned_p (op0l, op2h)) |
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897 { |
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898 emit_move_insn (scratch, op0l); |
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899 op2h = scratch; |
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900 } |
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901 |
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902 if (!rtx_equal_p (op0l, op1l)) |
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903 { |
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904 gcc_assert (TARGET_AM33); |
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905 if (!REG_P (op2l)) |
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906 { |
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907 emit_move_insn (op0l, op1l); |
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908 op1l = op0l; |
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909 } |
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910 } |
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911 emit_insn (gen_subsi3_flags (op0l, op1l, op2l)); |
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912 |
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913 if (!rtx_equal_p (op0h, op1h)) |
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914 { |
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915 gcc_assert (TARGET_AM33); |
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916 if (!REG_P (op2h)) |
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917 { |
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918 emit_move_insn (op0h, op1h); |
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919 op1h = op0h; |
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920 } |
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921 } |
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922 emit_insn (gen_subc_internal (op0h, op1h, op2h)); |
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923 DONE; |
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924 } |
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925 [(set_attr "isa" "*,am33")] |
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926 ) |
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927 |
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928 ;; The following pattern is generated by combine when it proves that one |
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929 ;; of the inputs to the low-part of the double-word sub is zero, and thus |
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930 ;; no carry is generated into the high-part. |
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931 |
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932 (define_insn_and_split "*subdi3_degenerate" |
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933 [(set (match_operand:SI 0 "register_operand" "=&r,&r") |
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934 (match_operand:SI 2 "nonmemory_operand" " 0, 0")) |
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935 (set (match_operand:SI 1 "register_operand" "=r , r") |
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936 (minus:SI (match_operand:SI 3 "register_operand" " 1, r") |
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937 (match_operand:SI 4 "nonmemory_operand" " ri, r"))) |
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938 (clobber (reg:CC CC_REG))] |
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939 "" |
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940 "#" |
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941 "" |
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942 [(const_int 0)] |
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943 { |
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944 rtx scratch = NULL_RTX; |
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945 if (!rtx_equal_p (operands[0], operands[2])) |
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946 { |
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947 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])); |
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948 if (reg_overlap_mentioned_p (operands[0], operands[3]) |
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949 || reg_overlap_mentioned_p (operands[0], operands[4])) |
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950 { |
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951 scratch = gen_reg_rtx (SImode); |
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952 emit_move_insn (scratch, operands[2]); |
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953 } |
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954 else |
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955 emit_move_insn (operands[0], operands[2]); |
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956 } |
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957 emit_insn (gen_subsi3 (operands[1], operands[3], operands[4])); |
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958 if (scratch) |
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959 emit_move_insn (operands[0], scratch); |
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960 DONE; |
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961 }) |
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962 |
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963 (define_insn_and_split "negsi2" |
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964 [(set (match_operand:SI 0 "register_operand" "=D,&r") |
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965 (neg:SI (match_operand:SI 1 "register_operand" " 0, r"))) |
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966 (clobber (reg:CC CC_REG))] |
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967 "" |
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968 "#" |
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969 "&& reload_completed" |
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970 [(const_int 0)] |
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971 { |
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972 /* Recall that twos-compliment is ones-compliment plus one. When |
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973 allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33) |
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974 this is 3+3 bytes. |
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975 |
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976 For AM33, it would have been possible to load zero and use the |
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977 three-address subtract to have a total size of 3+4*N bytes for |
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978 multiple negations, plus increased throughput. Not attempted here. */ |
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979 |
0 | 980 if (true_regnum (operands[0]) == true_regnum (operands[1])) |
67
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981 { |
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982 emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); |
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983 emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx)); |
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984 } |
0 | 985 else |
986 { | |
67
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987 emit_move_insn (operands[0], const0_rtx); |
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988 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1])); |
0 | 989 } |
990 DONE; | |
67
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991 }) |
0 | 992 |
993 ;; ---------------------------------------------------------------------- | |
994 ;; MULTIPLY INSTRUCTIONS | |
995 ;; ---------------------------------------------------------------------- | |
996 | |
67
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997 ;; ??? Note that AM33 has a third multiply variant that puts the high part |
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998 ;; into the MDRQ register, however this variant also constrains the inputs |
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999 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering |
111 | 1000 ;; the existence of the 4-operand multiply. Nor is there a set of divide |
67
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1001 ;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would |
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1002 ;; have been very handy for starting udivmodsi4... |
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1003 |
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1004 (define_expand "mulsidi3" |
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1005 [(set (match_operand:DI 0 "register_operand" "") |
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1006 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) |
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1007 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))] |
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1008 "" |
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1009 { |
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1010 emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]), |
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1011 gen_highpart (SImode, operands[0]), |
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1012 operands[1], operands[2])); |
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1013 DONE; |
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1014 }) |
0 | 1015 |
67
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1016 (define_insn "mulsidi3_internal" |
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parents:
55
diff
changeset
|
1017 [(set (match_operand:SI 0 "register_operand" "=D,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1018 (mult:SI (match_operand:SI 2 "register_operand" "%0,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1019 (match_operand:SI 3 "register_operand" " D,r"))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1020 (set (match_operand:SI 1 "register_operand" "=z,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1021 (truncate:SI |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1022 (ashiftrt:DI |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1023 (mult:DI (sign_extend:DI (match_dup 2)) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1024 (sign_extend:DI (match_dup 3))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1025 (const_int 32)))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1026 (clobber (reg:CC CC_REG))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1027 "" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1028 { |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1029 if (which_alternative == 1) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1030 return "mul %2,%3,%1,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1031 else if (TARGET_MULT_BUG) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1032 return "nop\;nop\;mul %3,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1033 else |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1034 return "mul %3,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1035 } |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1036 [(set_attr "isa" "*,am33") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1037 (set (attr "timings") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1038 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1039 ) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1040 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1041 (define_expand "umulsidi3" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1042 [(set (match_operand:DI 0 "register_operand" "") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1043 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1044 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1045 (clobber (reg:CC CC_REG))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1046 "" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1047 { |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1048 emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]), |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1049 gen_highpart (SImode, operands[0]), |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1050 operands[1], operands[2])); |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1051 DONE; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1052 }) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1053 |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1054 (define_insn "umulsidi3_internal" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1055 [(set (match_operand:SI 0 "register_operand" "=D,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1056 (mult:SI (match_operand:SI 2 "register_operand" "%0,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1057 (match_operand:SI 3 "register_operand" " D,r"))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1058 (set (match_operand:SI 1 "register_operand" "=z,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1059 (truncate:SI |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1060 (lshiftrt:DI |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1061 (mult:DI (zero_extend:DI (match_dup 2)) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1062 (zero_extend:DI (match_dup 3))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1063 (const_int 32)))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1064 (clobber (reg:CC CC_REG))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1065 "" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1066 { |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1067 if (which_alternative == 1) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1068 return "mulu %2,%3,%1,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1069 else if (TARGET_MULT_BUG) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1070 return "nop\;nop\;mulu %3,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1071 else |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1072 return "mulu %3,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1073 } |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1074 [(set_attr "isa" "*,am33") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1075 (set (attr "timings") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1076 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1077 ) |
0 | 1078 |
1079 (define_expand "mulsi3" | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1080 [(parallel [(set (match_operand:SI 0 "register_operand") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1081 (mult:SI (match_operand:SI 1 "register_operand") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1082 (match_operand:SI 2 "reg_or_am33_const_operand"))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1083 (clobber (match_scratch:SI 3)) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1084 (clobber (reg:CC CC_REG))])] |
0 | 1085 "" |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1086 ) |
0 | 1087 |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1088 (define_insn "*mulsi3" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1089 [(set (match_operand:SI 0 "register_operand" "=D, r,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1090 (mult:SI (match_operand:SI 2 "register_operand" "%0, 0,r") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1091 (match_operand:SI 3 "reg_or_am33_const_operand" " D,ri,r"))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1092 (clobber (match_scratch:SI 1 "=z, z,r")) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1093 (clobber (reg:CC CC_REG))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1094 "" |
0 | 1095 { |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1096 if (which_alternative == 2) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1097 return "mul %2,%3,%1,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1098 else if (TARGET_MULT_BUG) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1099 return "nop\;nop\;mul %3,%0"; |
0 | 1100 else |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1101 return "mul %3,%0"; |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1102 } |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1103 [(set_attr "isa" "*,am33,am33") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1104 (set (attr "timings") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1105 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1106 ) |
0 | 1107 |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1108 (define_expand "udivmodsi4" |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1109 [(parallel [(set (match_operand:SI 0 "register_operand") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1110 (udiv:SI (match_operand:SI 1 "register_operand") |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1111 (match_operand:SI 2 "register_operand"))) |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1112 (set (match_operand:SI 3 "register_operand") |
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1113 (umod:SI (match_dup 1) (match_dup 2))) |
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1114 (use (const_int 0)) |
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1115 (clobber (reg:CC CC_REG))])] |
0 | 1116 "" |
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1117 ) |
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1118 |
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1119 ;; Note the trick to get reload to put the zero into the MDR register, |
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1120 ;; rather than exposing the load early and letting CSE or someone try |
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1121 ;; to share the zeros between division insns. Which tends to result |
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1122 ;; in sequences like 0->r0->d0->mdr. |
0 | 1123 |
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1124 (define_insn "*udivmodsi4" |
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1125 [(set (match_operand:SI 0 "register_operand" "=D") |
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1126 (udiv:SI (match_operand:SI 2 "register_operand" " 0") |
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1127 (match_operand:SI 3 "register_operand" " D"))) |
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1128 (set (match_operand:SI 1 "register_operand" "=z") |
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1129 (umod:SI (match_dup 2) (match_dup 3))) |
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1130 (use (match_operand:SI 4 "nonmemory_operand" " 1")) |
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1131 (clobber (reg:CC CC_REG))] |
0 | 1132 "" |
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1133 "divu %3,%0" |
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1134 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1135 (const_int 3839) (const_int 4243)))] |
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1136 ) |
0 | 1137 |
67
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1138 (define_expand "divmodsi4" |
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1139 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1140 (div:SI (match_operand:SI 1 "register_operand" "") |
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1141 (match_operand:SI 2 "register_operand" ""))) |
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1142 (set (match_operand:SI 3 "register_operand" "") |
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1143 (mod:SI (match_dup 1) (match_dup 2))) |
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1144 (use (match_dup 4)) |
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1145 (clobber (reg:CC CC_REG))])] |
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1146 "" |
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1147 { |
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1148 operands[4] = gen_reg_rtx (SImode); |
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1149 emit_insn (gen_ext_internal (operands[4], operands[1])); |
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1150 }) |
0 | 1151 |
67
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1152 ;; ??? Ideally we'd represent this via shift, but it seems like adding a |
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1153 ;; special-case pattern for (ashiftrt x 31) is just as likely to result |
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1154 ;; in poor register allocation choices. |
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1155 (define_insn "ext_internal" |
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1156 [(set (match_operand:SI 0 "register_operand" "=z") |
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1157 (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))] |
0 | 1158 "" |
67
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1159 "ext %1" |
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1160 ) |
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1161 |
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1162 (define_insn "*divmodsi4" |
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1163 [(set (match_operand:SI 0 "register_operand" "=D") |
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1164 (div:SI (match_operand:SI 2 "register_operand" " 0") |
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1165 (match_operand:SI 3 "register_operand" " D"))) |
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1166 (set (match_operand:SI 1 "register_operand" "=z") |
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1167 (mod:SI (match_dup 2) (match_dup 3))) |
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1168 (use (match_operand:SI 4 "register_operand" " 1")) |
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1169 (clobber (reg:CC CC_REG))] |
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1170 "" |
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1171 "div %3,%0"; |
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1172 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1173 (const_int 3839) (const_int 4243)))] |
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1174 ) |
0 | 1175 |
1176 | |
1177 ;; ---------------------------------------------------------------------- | |
1178 ;; AND INSTRUCTIONS | |
1179 ;; ---------------------------------------------------------------------- | |
1180 | |
67
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1181 (define_insn "andsi3" |
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1182 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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1183 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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1184 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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1185 (clobber (reg:CC CC_REG))] |
0 | 1186 "" |
67
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1187 "@ |
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1188 and %2,%0 |
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1189 and %2,%0 |
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1190 and %2,%1,%0" |
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1191 [(set_attr "isa" "*,*,am33") |
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1192 (set_attr "liw" "*,op1,*") |
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1193 (set_attr "liw_op" "and") |
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1194 (set_attr "timings" "22,11,11")] |
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1195 ) |
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1196 |
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1197 (define_insn "*andsi3_flags" |
111 | 1198 [(set (reg CC_REG) |
1199 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") | |
1200 (match_operand:SI 2 "nonmemory_operand" " i,D,r")) | |
1201 (const_int 0))) | |
1202 (set (match_operand:SI 0 "register_operand" "=D,D,r") | |
1203 (and:SI (match_dup 1) (match_dup 2)))] | |
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1204 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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1205 "@ |
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1206 and %2,%0 |
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1207 and %2,%0 |
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1208 and %2,%1,%0" |
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1209 [(set_attr "isa" "*,*,am33") |
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1210 (set_attr "timings" "22,11,11")] |
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1211 ) |
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1212 |
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1213 ;; Make sure we generate extensions instead of ANDs. |
0 | 1214 |
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1215 (define_split |
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1216 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1217 (and:SI (match_operand:SI 1 "register_operand" "") |
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1218 (const_int 255))) |
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1219 (clobber (reg:CC CC_REG))])] |
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1220 "" |
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1221 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] |
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1222 { operands[1] = gen_lowpart (QImode, operands[1]); } |
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1223 ) |
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1224 |
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|
1225 (define_split |
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1226 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1227 (and:SI (match_operand:SI 1 "register_operand" "") |
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1228 (const_int 65535))) |
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1229 (clobber (reg:CC CC_REG))])] |
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1230 "" |
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1231 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] |
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1232 { operands[1] = gen_lowpart (HImode, operands[1]); } |
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1233 ) |
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1234 |
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1235 ;; Split AND by an appropriate constant into two shifts. Recall that |
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1236 ;; operations with a full 32-bit immediate require an extra cycle, so |
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1237 ;; this is a size optimization with no speed penalty. This only applies |
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1238 ;; do DATA_REGS; the shift insns that AM33 adds are too large for a win. |
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1239 |
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1240 (define_split |
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1241 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1242 (and:SI (match_dup 0) |
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1243 (match_operand:SI 1 "const_int_operand" ""))) |
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1244 (clobber (reg:CC CC_REG))])] |
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1245 "reload_completed |
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1246 && REGNO_DATA_P (true_regnum (operands[0]), 1) |
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1247 && mn10300_split_and_operand_count (operands[1]) != 0" |
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1248 [(const_int 0)] |
0 | 1249 { |
67
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1250 int count = mn10300_split_and_operand_count (operands[1]); |
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1251 if (count > 0) |
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1252 { |
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1253 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count))); |
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1254 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count))); |
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1255 } |
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1256 else |
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1257 { |
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1258 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count))); |
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1259 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count))); |
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1260 } |
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1261 DONE; |
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1262 }) |
0 | 1263 |
1264 ;; ---------------------------------------------------------------------- | |
1265 ;; OR INSTRUCTIONS | |
1266 ;; ---------------------------------------------------------------------- | |
1267 | |
67
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1268 (define_insn "iorsi3" |
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1269 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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1270 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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1271 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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1272 (clobber (reg:CC CC_REG))] |
0 | 1273 "" |
67
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|
1274 "@ |
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|
1275 or %2,%0 |
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|
1276 or %2,%0 |
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|
1277 or %2,%1,%0" |
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|
1278 [(set_attr "isa" "*,*,am33") |
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|
1279 (set_attr "liw" "*,op1,*") |
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|
1280 (set_attr "liw_op" "or") |
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|
1281 (set_attr "timings" "22,11,11")] |
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|
1282 ) |
0 | 1283 |
67
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|
1284 (define_insn "*iorsi3_flags" |
111 | 1285 [(set (reg CC_REG) |
1286 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") | |
1287 (match_operand:SI 2 "nonmemory_operand" " i,D,r")) | |
1288 (const_int 0))) | |
1289 (set (match_operand:SI 0 "register_operand" "=D,D,r") | |
1290 (ior:SI (match_dup 1) (match_dup 2)))] | |
67
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|
1291 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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|
1292 "@ |
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|
1293 or %2,%0 |
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|
1294 or %2,%0 |
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|
1295 or %2,%1,%0" |
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|
1296 [(set_attr "isa" "*,*,am33") |
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|
1297 (set_attr "timings" "22,11,11")] |
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|
1298 ) |
0 | 1299 |
1300 ;; ---------------------------------------------------------------------- | |
1301 ;; XOR INSTRUCTIONS | |
1302 ;; ---------------------------------------------------------------------- | |
1303 | |
67
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|
1304 (define_insn "xorsi3" |
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|
1305 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
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|
1306 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") |
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|
1307 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) |
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|
1308 (clobber (reg:CC CC_REG))] |
0 | 1309 "" |
67
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|
1310 "@ |
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|
1311 xor %2,%0 |
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|
1312 xor %2,%0 |
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|
1313 xor %2,%1,%0" |
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|
1314 [(set_attr "isa" "*,*,am33") |
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|
1315 (set_attr "liw" "*,op1,*") |
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|
1316 (set_attr "liw_op" "xor") |
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|
1317 (set_attr "timings" "22,11,11")] |
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|
1318 ) |
0 | 1319 |
67
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|
1320 (define_insn "*xorsi3_flags" |
111 | 1321 [(set (reg CC_REG) |
1322 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") | |
1323 (match_operand:SI 2 "nonmemory_operand" " i,D,r")) | |
1324 (const_int 0))) | |
1325 (set (match_operand:SI 0 "register_operand" "=D,D,r") | |
1326 (xor:SI (match_dup 1) (match_dup 2)))] | |
67
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|
1327 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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|
1328 "@ |
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|
1329 xor %2,%0 |
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|
1330 xor %2,%0 |
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|
1331 xor %2,%1,%0" |
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1332 [(set_attr "isa" "*,*,am33") |
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1333 (set_attr "timings" "22,11,11")] |
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1334 ) |
0 | 1335 |
1336 ;; ---------------------------------------------------------------------- | |
1337 ;; NOT INSTRUCTIONS | |
1338 ;; ---------------------------------------------------------------------- | |
1339 | |
67
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1340 (define_insn "one_cmplsi2" |
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1341 [(set (match_operand:SI 0 "register_operand" "=D") |
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1342 (not:SI (match_operand:SI 1 "register_operand" " 0"))) |
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1343 (clobber (reg:CC CC_REG))] |
0 | 1344 "" |
1345 "not %0" | |
67
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1346 ) |
0 | 1347 |
67
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1348 (define_insn "*one_cmplsi2_flags" |
111 | 1349 [(set (reg CC_REG) |
1350 (compare (not:SI (match_operand:SI 1 "register_operand" "0")) | |
1351 (const_int 0))) | |
1352 (set (match_operand:SI 0 "register_operand" "=D") | |
1353 (not:SI (match_dup 1)))] | |
67
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1354 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" |
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1355 "not %0" |
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1356 ) |
0 | 1357 |
1358 ;; ---------------------------------------------------------------------- | |
67
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1359 ;; COMPARE AND BRANCH INSTRUCTIONS |
0 | 1360 ;; ---------------------------------------------------------------------- |
1361 | |
67
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1362 ;; We expand the comparison into a single insn so that it will not be split |
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1363 ;; up by reload. |
55
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1364 (define_expand "cbranchsi4" |
67
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1365 [(set (pc) |
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1366 (if_then_else |
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1367 (match_operator 0 "ordered_comparison_operator" |
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1368 [(match_operand:SI 1 "register_operand") |
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1369 (match_operand:SI 2 "nonmemory_operand")]) |
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1370 (label_ref (match_operand 3 "")) |
55
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1371 (pc)))] |
0 | 1372 "" |
67
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1373 "" |
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1374 ) |
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1375 |
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1376 (define_insn_and_split "*cbranchsi4_cmp" |
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1377 [(set (pc) |
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1378 (if_then_else (match_operator 3 "ordered_comparison_operator" |
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1379 [(match_operand:SI 0 "register_operand" "r") |
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1380 (match_operand:SI 1 "nonmemory_operand" "ri")]) |
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1381 (match_operand 2 "label_ref_operand" "") |
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1382 (pc)))] |
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1383 "" |
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1384 "#" |
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1385 "reload_completed" |
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1386 [(const_int 0)] |
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1387 { |
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1388 mn10300_split_cbranch (CCmode, operands[3], operands[2]); |
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1389 DONE; |
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1390 }) |
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1391 |
111 | 1392 (define_insn "cmpsi" |
67
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1393 [(set (reg CC_REG) |
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1394 (compare (match_operand:SI 0 "register_operand" "r,r,r") |
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1395 (match_operand:SI 1 "nonmemory_operand" "r,O,i")))] |
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1396 "reload_completed" |
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1397 { |
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1398 /* The operands of CMP must be distinct registers. In the case where |
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1399 we've failed to optimize the comparison of a register to itself, we |
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1400 must use another method to set the Z flag. We can achieve this |
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1401 effect with a BTST 0,D0. This will not alter the contents of D0; |
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1402 the use of d0 is arbitrary; any data register would work. */ |
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1403 if (rtx_equal_p (operands[0], operands[1])) |
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1404 return "btst 0,d0"; |
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1405 else |
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1406 return "cmp %1,%0"; |
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1407 } |
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1408 [(set_attr_alternative "timings" |
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1409 [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22)) |
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1410 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22)) |
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1411 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))]) |
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1412 (set_attr "liw" "either,either,*") |
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1413 (set_attr "liw_op" "cmp")] |
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1414 ) |
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1415 |
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1416 (define_insn "*integer_conditional_branch" |
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1417 [(set (pc) |
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1418 (if_then_else (match_operator 0 "comparison_operator" |
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1419 [(match_operand 2 "int_mode_flags" "") |
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1420 (const_int 0)]) |
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1421 (label_ref (match_operand 1 "" "")) |
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1422 (pc)))] |
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1423 "reload_completed" |
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|
1424 "b%b0 %1" |
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1425 ) |
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1426 |
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1427 (define_insn_and_split "*cbranchsi4_btst" |
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1428 [(set (pc) |
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1429 (if_then_else |
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1430 (match_operator 3 "CCZN_comparison_operator" |
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1431 [(and:SI (match_operand:SI 0 "register_operand" "D") |
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1432 (match_operand:SI 1 "immediate_operand" "i")) |
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1433 (const_int 0)]) |
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1434 (match_operand 2 "label_ref_operand" "") |
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1435 (pc)))] |
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1436 "" |
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1437 "#" |
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1438 "reload_completed" |
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|
1439 [(const_int 0)] |
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1440 { |
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1441 mn10300_split_cbranch (CCZNmode, operands[3], operands[2]); |
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1442 DONE; |
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1443 }) |
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1444 |
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1445 (define_insn "*btstsi" |
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1446 [(set (reg:CCZN CC_REG) |
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1447 (compare:CCZN |
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1448 (and:SI (match_operand:SI 0 "register_operand" "D") |
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1449 (match_operand:SI 1 "immediate_operand" "i")) |
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1450 (const_int 0)))] |
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|
1451 "reload_completed" |
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|
1452 "btst %1,%0" |
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1453 ) |
0 | 1454 |
55
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1455 (define_expand "cbranchsf4" |
67
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1456 [(set (pc) |
55
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1457 (if_then_else |
67
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1458 (match_operator 0 "ordered_comparison_operator" |
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1459 [(match_operand:SF 1 "register_operand") |
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1460 (match_operand:SF 2 "nonmemory_operand")]) |
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1461 (label_ref (match_operand 3 "")) |
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1462 (pc)))] |
55
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|
1463 "TARGET_AM33_2" |
67
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1464 "" |
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1465 ) |
0 | 1466 |
67
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|
1467 (define_insn_and_split "*cbranchsf4_cmp" |
0 | 1468 [(set (pc) |
67
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|
1469 (if_then_else (match_operator 3 "ordered_comparison_operator" |
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1470 [(match_operand:SF 0 "register_operand" "f") |
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1471 (match_operand:SF 1 "nonmemory_operand" "fF")]) |
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|
1472 (match_operand 2 "label_ref_operand" "") |
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|
1473 (pc))) |
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|
1474 ] |
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|
1475 "TARGET_AM33_2" |
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|
1476 "#" |
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|
1477 "&& reload_completed" |
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1478 [(const_int 0)] |
0 | 1479 { |
67
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|
1480 mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]); |
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|
1481 DONE; |
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1482 }) |
0 | 1483 |
67
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|
1484 (define_insn "*am33_cmpsf" |
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1485 [(set (reg:CC_FLOAT CC_REG) |
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|
1486 (compare:CC_FLOAT (match_operand:SF 0 "register_operand" "f") |
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1487 (match_operand:SF 1 "nonmemory_operand" "fF")))] |
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|
1488 "TARGET_AM33_2 && reload_completed" |
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|
1489 "fcmp %1, %0" |
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1490 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1491 (const_int 17) (const_int 25)))] |
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|
1492 ) |
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|
1493 |
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|
1494 (define_insn "*float_conditional_branch" |
0 | 1495 [(set (pc) |
67
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|
1496 (if_then_else (match_operator 0 "comparison_operator" |
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1497 [(reg:CC_FLOAT CC_REG) (const_int 0)]) |
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|
1498 (label_ref (match_operand 1 "" "")) |
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|
1499 (pc)))] |
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|
1500 "TARGET_AM33_2 && reload_completed" |
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|
1501 "fb%b0 %1" |
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1502 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1503 (const_int 44) (const_int 33)))] |
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|
1504 ) |
0 | 1505 |
1506 ;; Unconditional and other jump instructions. | |
1507 | |
1508 (define_insn "jump" | |
1509 [(set (pc) | |
1510 (label_ref (match_operand 0 "" "")))] | |
1511 "" | |
1512 "jmp %l0" | |
67
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|
1513 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1514 (const_int 11) (const_int 44)))] |
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|
1515 ) |
0 | 1516 |
1517 (define_insn "indirect_jump" | |
1518 [(set (pc) (match_operand:SI 0 "register_operand" "a"))] | |
1519 "" | |
1520 "jmp (%0)" | |
67
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|
1521 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1522 (const_int 11) (const_int 33)))] |
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|
1523 ) |
0 | 1524 |
1525 (define_expand "builtin_setjmp_receiver" | |
1526 [(match_operand 0 "" "")] | |
1527 "flag_pic" | |
1528 { | |
67
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|
1529 emit_insn (gen_load_pic ()); |
0 | 1530 DONE; |
67
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|
1531 }) |
0 | 1532 |
1533 (define_expand "casesi" | |
67
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|
1534 [(match_operand:SI 0 "register_operand") |
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|
1535 (match_operand:SI 1 "immediate_operand") |
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|
1536 (match_operand:SI 2 "immediate_operand") |
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|
1537 (match_operand 3 "" "") (match_operand 4 "")] |
0 | 1538 "" |
1539 { | |
1540 rtx table = gen_reg_rtx (SImode); | |
1541 rtx index = gen_reg_rtx (SImode); | |
1542 rtx addr = gen_reg_rtx (Pmode); | |
55
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diff
changeset
|
1543 rtx test; |
0 | 1544 |
1545 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3])); | |
67
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|
1546 emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1])))); |
55
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diff
changeset
|
1547 test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]); |
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diff
changeset
|
1548 emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4])); |
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|
1549 |
67
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|
1550 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
0 | 1551 emit_move_insn (addr, gen_rtx_MEM (SImode, |
1552 gen_rtx_PLUS (SImode, table, index))); | |
1553 if (flag_pic) | |
67
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diff
changeset
|
1554 emit_insn (gen_addsi3 (addr, addr, table)); |
0 | 1555 |
1556 emit_jump_insn (gen_tablejump (addr, operands[3])); | |
1557 DONE; | |
67
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|
1558 }) |
0 | 1559 |
1560 (define_insn "tablejump" | |
1561 [(set (pc) (match_operand:SI 0 "register_operand" "a")) | |
1562 (use (label_ref (match_operand 1 "" "")))] | |
1563 "" | |
1564 "jmp (%0)" | |
67
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|
1565 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
1566 (const_int 11) (const_int 33)))] |
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|
1567 ) |
0 | 1568 |
1569 ;; Call subroutine with no return value. | |
1570 | |
1571 (define_expand "call" | |
67
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|
1572 [(call (match_operand:QI 0 "general_operand") |
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1573 (match_operand:SI 1 "general_operand"))] |
0 | 1574 "" |
1575 { | |
67
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1576 rtx fn = XEXP (operands[0], 0); |
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1577 |
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1578 if (flag_pic && GET_CODE (fn) == SYMBOL_REF) |
0 | 1579 { |
67
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1580 if (MN10300_GLOBAL_P (fn)) |
0 | 1581 { |
1582 /* The PLT code won't run on AM30, but then, there's no | |
1583 shared library support for AM30 either, so we just assume | |
1584 the linker is going to adjust all @PLT relocs to the | |
1585 actual symbols. */ | |
1586 emit_use (pic_offset_table_rtx); | |
67
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1587 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT); |
0 | 1588 } |
1589 else | |
67
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1590 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC); |
0 | 1591 } |
67
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1592 if (! call_address_operand (fn, VOIDmode)) |
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1593 fn = force_reg (SImode, fn); |
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1594 |
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1595 XEXP (operands[0], 0) = fn; |
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1596 }) |
0 | 1597 |
67
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1598 (define_insn "*call_internal" |
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1599 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S")) |
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1600 (match_operand:SI 1 "" ""))] |
0 | 1601 "" |
67
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1602 "@ |
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1603 calls %C0 |
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1604 call %C0,[],0" |
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1605 [(set_attr_alternative "timings" |
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1606 [(if_then_else (eq_attr "cpu" "am34") |
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1607 (const_int 33) (const_int 44)) |
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1608 (if_then_else (eq_attr "cpu" "am34") |
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1609 (const_int 55) (const_int 33)) |
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1610 ]) |
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1611 ] |
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1612 ) |
0 | 1613 |
1614 ;; Call subroutine, returning value in operand 0 | |
1615 ;; (which must be a hard register). | |
1616 | |
1617 (define_expand "call_value" | |
67
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1618 [(set (match_operand 0 "") |
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1619 (call (match_operand:QI 1 "general_operand") |
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1620 (match_operand:SI 2 "general_operand")))] |
0 | 1621 "" |
1622 { | |
67
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1623 rtx fn = XEXP (operands[1], 0); |
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1624 |
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1625 if (flag_pic && GET_CODE (fn) == SYMBOL_REF) |
0 | 1626 { |
67
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1627 if (MN10300_GLOBAL_P (fn)) |
0 | 1628 { |
1629 /* The PLT code won't run on AM30, but then, there's no | |
1630 shared library support for AM30 either, so we just assume | |
1631 the linker is going to adjust all @PLT relocs to the | |
1632 actual symbols. */ | |
1633 emit_use (pic_offset_table_rtx); | |
67
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1634 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT); |
0 | 1635 } |
1636 else | |
67
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1637 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC); |
0 | 1638 } |
67
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1639 if (! call_address_operand (fn, VOIDmode)) |
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1640 fn = force_reg (SImode, fn); |
0 | 1641 |
67
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1642 XEXP (operands[1], 0) = fn; |
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1643 }) |
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1644 |
0 | 1645 (define_insn "call_value_internal" |
67
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1646 [(set (match_operand 0 "" "") |
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1647 (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S")) |
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1648 (match_operand:SI 2 "" "")))] |
0 | 1649 "" |
67
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1650 "@ |
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1651 calls %C1 |
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1652 call %C1,[],0" |
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1653 [(set_attr_alternative "timings" |
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1654 [(if_then_else (eq_attr "cpu" "am34") |
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1655 (const_int 33) (const_int 44)) |
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1656 (if_then_else (eq_attr "cpu" "am34") |
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1657 (const_int 55) (const_int 33)) |
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|
1658 ]) |
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|
1659 ] |
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1660 ) |
0 | 1661 |
1662 (define_expand "untyped_call" | |
67
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1663 [(parallel [(call (match_operand 0 "") |
0 | 1664 (const_int 0)) |
67
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|
1665 (match_operand 1 "") |
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1666 (match_operand 2 "")])] |
0 | 1667 "" |
1668 { | |
1669 int i; | |
1670 | |
1671 emit_call_insn (gen_call (operands[0], const0_rtx)); | |
1672 | |
1673 for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
1674 { | |
1675 rtx set = XVECEXP (operands[2], 0, i); | |
1676 emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
1677 } | |
1678 DONE; | |
67
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1679 }) |
0 | 1680 |
1681 (define_insn "nop" | |
1682 [(const_int 0)] | |
1683 "" | |
1684 "nop" | |
67
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1685 ) |
0 | 1686 |
1687 ;; ---------------------------------------------------------------------- | |
1688 ;; EXTEND INSTRUCTIONS | |
1689 ;; ---------------------------------------------------------------------- | |
1690 | |
67
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|
1691 (define_insn "zero_extendqisi2" |
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1692 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
0 | 1693 (zero_extend:SI |
67
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1694 (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))] |
0 | 1695 "" |
1696 "@ | |
67
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|
1697 extbu %0 |
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|
1698 movbu %1,%0 |
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|
1699 extbu %1,%0" |
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1700 [(set_attr "isa" "*,*,am33") |
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1701 (set_attr_alternative "timings" |
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1702 [(const_int 11) |
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1703 (if_then_else (eq_attr "cpu" "am34") |
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1704 (const_int 13) (const_int 24)) |
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1705 (const_int 11) |
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|
1706 ])] |
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1707 ) |
0 | 1708 |
67
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|
1709 (define_insn "zero_extendhisi2" |
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1710 [(set (match_operand:SI 0 "register_operand" "=D,D,r") |
0 | 1711 (zero_extend:SI |
67
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1712 (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))] |
0 | 1713 "" |
1714 "@ | |
67
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|
1715 exthu %0 |
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|
1716 movhu %1,%0 |
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|
1717 exthu %1,%0" |
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1718 [(set_attr "isa" "*,*,am33") |
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|
1719 (set_attr_alternative "timings" |
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1720 [(const_int 11) |
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1721 (if_then_else (eq_attr "cpu" "am34") |
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1722 (const_int 13) (const_int 24)) |
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1723 (const_int 11)])] |
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1724 ) |
0 | 1725 |
67
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1726 (define_insn "extendqisi2" |
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1727 [(set (match_operand:SI 0 "register_operand" "=D,r") |
0 | 1728 (sign_extend:SI |
67
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1729 (match_operand:QI 1 "register_operand" "0,r")))] |
0 | 1730 "" |
1731 "@ | |
67
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1732 extb %0 |
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1733 extb %1,%0" |
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1734 [(set_attr "isa" "*,am33")] |
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1735 ) |
0 | 1736 |
67
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1737 (define_insn "extendhisi2" |
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1738 [(set (match_operand:SI 0 "register_operand" "=D,r") |
0 | 1739 (sign_extend:SI |
67
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1740 (match_operand:HI 1 "register_operand" "0,r")))] |
0 | 1741 "" |
1742 "@ | |
67
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1743 exth %0 |
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1744 exth %1,%0" |
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1745 [(set_attr "isa" "*,am33")] |
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1746 ) |
0 | 1747 |
1748 ;; ---------------------------------------------------------------------- | |
1749 ;; SHIFTS | |
1750 ;; ---------------------------------------------------------------------- | |
1751 | |
67
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1752 (define_insn "ashlsi3" |
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1753 [(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,D,r") |
0 | 1754 (ashift:SI |
67
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1755 (match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,0,r") |
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1756 (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,O,i,r"))) |
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1757 (clobber (reg:CC CC_REG))] |
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1758 "" |
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1759 "@ |
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1760 add %0,%0 |
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1761 asl2 %0 |
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1762 asl2 %0\;add %0,%0 |
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1763 asl2 %0\;asl2 %0 |
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1764 asl %S2,%0 |
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1765 asl %S2,%0 |
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1766 asl %S2,%0 |
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1767 asl %2,%1,%0" |
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1768 [(set_attr "isa" "*,*,*,*,*,*,*,am33") |
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1769 (set_attr "liw" "op2,op2,op2,op2,op2,op2,*,*") |
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1770 (set_attr "liw_op" "asl") |
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1771 (set_attr "timings" "11,11,22,22,11,11,11,11")] |
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1772 ) |
0 | 1773 |
67
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1774 (define_insn "lshrsi3" |
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1775 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r") |
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1776 (lshiftrt:SI |
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1777 (match_operand:SI 1 "register_operand" "0,0,0,r") |
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1778 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r"))) |
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1779 (clobber (reg:CC CC_REG))] |
0 | 1780 "" |
1781 "@ | |
67
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1782 lsr %S2,%0 |
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1783 lsr %S2,%0 |
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1784 lsr %S2,%0 |
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1785 lsr %2,%1,%0" |
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1786 [(set_attr "isa" "*,*,*,am33") |
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1787 (set_attr "liw" "op2,op2,*,*") |
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1788 (set_attr "liw_op" "lsr")] |
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1789 ) |
0 | 1790 |
67
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1791 (define_insn "ashrsi3" |
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1792 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r") |
0 | 1793 (ashiftrt:SI |
67
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1794 (match_operand:SI 1 "register_operand" "0,0,0,r") |
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1795 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r"))) |
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1796 (clobber (reg:CC CC_REG))] |
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1797 "" |
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1798 "@ |
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1799 asr %S2,%0 |
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1800 asr %S2,%0 |
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1801 asr %S2,%0 |
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1802 asr %2,%1,%0" |
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1803 [(set_attr "isa" "*,*,*,am33") |
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1804 (set_attr "liw" "op2,op2,*,*") |
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1805 (set_attr "liw_op" "asr")] |
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1806 ) |
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1807 |
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1808 ;; ---------------------------------------------------------------------- |
111 | 1809 ;; MISCELLANEOUS |
67
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1810 ;; ---------------------------------------------------------------------- |
0 | 1811 |
111 | 1812 ;; Note the use of the (const_int 0) when generating the insn that matches |
1813 ;; the bsch pattern. This ensures that the destination register is | |
1814 ;; initialised with 0 which will make the BSCH instruction set searching | |
1815 ;; at bit 31. | |
1816 ;; | |
1817 ;; The XOR in the instruction sequence below is there because the BSCH | |
1818 ;; instruction returns the bit number of the highest set bit and we want | |
1819 ;; the number of zero bits above that bit. The AM33 does not have a | |
1820 ;; reverse subtraction instruction, but we can use a simple xor instead | |
1821 ;; since we know that the top 27 bits are clear. | |
67
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1822 (define_expand "clzsi2" |
111 | 1823 [(parallel [(set (match_operand:SI 0 "register_operand") |
1824 (unspec:SI [(match_operand:SI 1 "register_operand") | |
67
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1825 (const_int 0)] UNSPEC_BSCH)) |
111 | 1826 (clobber (reg:CC CC_REG))]) |
1827 (parallel [(set (match_dup 0) | |
1828 (xor:SI (match_dup 0) | |
1829 (const_int 31))) | |
67
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1830 (clobber (reg:CC CC_REG))])] |
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|
1831 "TARGET_AM33" |
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1832 ) |
0 | 1833 |
67
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1834 (define_insn "*bsch" |
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1835 [(set (match_operand:SI 0 "register_operand" "=r") |
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1836 (unspec:SI [(match_operand:SI 1 "register_operand" "r") |
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1837 (match_operand:SI 2 "nonmemory_operand" "0")] |
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1838 UNSPEC_BSCH)) |
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1839 (clobber (reg:CC CC_REG))] |
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1840 "TARGET_AM33" |
111 | 1841 "bsch %1, %0" |
67
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1842 ) |
0 | 1843 |
1844 ;; ---------------------------------------------------------------------- | |
1845 ;; FP INSTRUCTIONS | |
1846 ;; ---------------------------------------------------------------------- | |
1847 | |
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1848 (define_insn "abssf2" |
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1849 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1850 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))] |
1851 "TARGET_AM33_2" | |
1852 "@ | |
1853 fabs %0 | |
1854 fabs %1, %0" | |
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1855 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1856 (const_int 17) (const_int 14)))] |
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1857 ) |
0 | 1858 |
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1859 (define_insn "negsf2" |
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1860 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1861 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))] |
1862 "TARGET_AM33_2" | |
1863 "@ | |
1864 fneg %0 | |
1865 fneg %1, %0" | |
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1866 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1867 (const_int 17) (const_int 14)))] |
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1868 ) |
0 | 1869 |
1870 (define_expand "sqrtsf2" | |
1871 [(set (match_operand:SF 0 "register_operand" "") | |
1872 (sqrt:SF (match_operand:SF 1 "register_operand" "")))] | |
1873 "TARGET_AM33_2 && flag_unsafe_math_optimizations" | |
1874 { | |
1875 rtx scratch = gen_reg_rtx (SFmode); | |
1876 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); | |
1877 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), | |
1878 scratch)); | |
1879 DONE; | |
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1880 }) |
0 | 1881 |
1882 (define_insn "rsqrtsf2" | |
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1883 [(set (match_operand:SF 0 "register_operand" "=f,f") |
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1884 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F") |
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1885 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f")))) |
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1886 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1887 "TARGET_AM33_2" |
1888 "@ | |
1889 frsqrt %0 | |
1890 frsqrt %1, %0" | |
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1891 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1892 (const_int 4753) (const_int 2327)))] |
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1893 ) |
0 | 1894 |
1895 (define_insn "addsf3" | |
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1896 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1897 (plus:SF (match_operand:SF 1 "register_operand" "%0,f") |
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1898 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1899 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1900 "TARGET_AM33_2" |
1901 "@ | |
1902 fadd %2, %0 | |
1903 fadd %2, %1, %0" | |
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1904 [(set_attr_alternative "timings" |
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1905 [(if_then_else (eq_attr "cpu" "am34") |
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1906 (const_int 17) (const_int 14)) |
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1907 (if_then_else (eq_attr "cpu" "am34") |
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1908 (const_int 17) (const_int 25)) |
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1909 ])] |
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1910 ) |
0 | 1911 |
1912 (define_insn "subsf3" | |
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1913 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1914 (minus:SF (match_operand:SF 1 "register_operand" "0,f") |
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1915 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1916 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1917 "TARGET_AM33_2" |
1918 "@ | |
1919 fsub %2, %0 | |
1920 fsub %2, %1, %0" | |
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1921 [(set_attr_alternative "timings" |
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1922 [(if_then_else (eq_attr "cpu" "am34") |
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1923 (const_int 17) (const_int 14)) |
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1924 (if_then_else (eq_attr "cpu" "am34") |
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1925 (const_int 17) (const_int 25)) |
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1926 ])] |
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1927 ) |
0 | 1928 |
1929 (define_insn "mulsf3" | |
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1930 [(set (match_operand:SF 0 "register_operand" "=f,f") |
0 | 1931 (mult:SF (match_operand:SF 1 "register_operand" "%0,f") |
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1932 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1933 (clobber (reg:CC_FLOAT CC_REG)) |
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1934 ] |
0 | 1935 "TARGET_AM33_2" |
1936 "@ | |
1937 fmul %2, %0 | |
1938 fmul %2, %1, %0" | |
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1939 [(set_attr_alternative "timings" |
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1940 [(if_then_else (eq_attr "cpu" "am34") |
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1941 (const_int 17) (const_int 14)) |
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1942 (if_then_else (eq_attr "cpu" "am34") |
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1943 (const_int 17) (const_int 25)) |
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1944 ])] |
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1945 ) |
0 | 1946 |
1947 (define_insn "divsf3" | |
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1948 [(set (match_operand:SF 0 "register_operand" "=f,f") |
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1949 (div:SF (match_operand:SF 1 "register_operand" "0,f") |
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1950 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) |
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1951 (clobber (reg:CC_FLOAT CC_REG))] |
0 | 1952 "TARGET_AM33_2" |
1953 "@ | |
1954 fdiv %2, %0 | |
1955 fdiv %2, %1, %0" | |
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1956 [(set_attr_alternative "timings" |
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1957 [(if_then_else (eq_attr "cpu" "am34") |
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1958 (const_int 2531) (const_int 1216)) |
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1959 (if_then_else (eq_attr "cpu" "am34") |
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1960 (const_int 2531) (const_int 1317)) |
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1961 ])] |
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1962 ) |
0 | 1963 |
67
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1964 (define_insn "fmasf4" |
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1965 [(set (match_operand:SF 0 "register_operand" "=c") |
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1966 (fma:SF (match_operand:SF 1 "register_operand" "f") |
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1967 (match_operand:SF 2 "register_operand" "f") |
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1968 (match_operand:SF 3 "register_operand" "f"))) |
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1969 (clobber (reg:CC_FLOAT CC_REG)) |
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1970 ] |
0 | 1971 "TARGET_AM33_2" |
1972 "fmadd %1, %2, %3, %0" | |
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1973 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1974 (const_int 17) (const_int 24)))] |
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1975 ) |
0 | 1976 |
67
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1977 (define_insn "fmssf4" |
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1978 [(set (match_operand:SF 0 "register_operand" "=c") |
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1979 (fma:SF (match_operand:SF 1 "register_operand" "f") |
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1980 (match_operand:SF 2 "register_operand" "f") |
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1981 (neg:SF (match_operand:SF 3 "register_operand" "f")))) |
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1982 (clobber (reg:CC_FLOAT CC_REG)) |
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1983 ] |
0 | 1984 "TARGET_AM33_2" |
1985 "fmsub %1, %2, %3, %0" | |
67
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1986 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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1987 (const_int 17) (const_int 24)))] |
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1988 ) |
0 | 1989 |
67
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1990 (define_insn "fnmasf4" |
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1991 [(set (match_operand:SF 0 "register_operand" "=c") |
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1992 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) |
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1993 (match_operand:SF 2 "register_operand" "f") |
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1994 (match_operand:SF 3 "register_operand" "f"))) |
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1995 (clobber (reg:CC_FLOAT CC_REG)) |
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1996 ] |
0 | 1997 "TARGET_AM33_2" |
1998 "fnmadd %1, %2, %3, %0" | |
67
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1999 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2000 (const_int 17) (const_int 24)))] |
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2001 ) |
0 | 2002 |
67
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2003 (define_insn "fnmssf4" |
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2004 [(set (match_operand:SF 0 "register_operand" "=c") |
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2005 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) |
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2006 (match_operand:SF 2 "register_operand" "f") |
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2007 (neg:SF (match_operand:SF 3 "register_operand" "f")))) |
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2008 (clobber (reg:CC_FLOAT CC_REG)) |
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2009 ] |
0 | 2010 "TARGET_AM33_2" |
2011 "fnmsub %1, %2, %3, %0" | |
67
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2012 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2013 (const_int 17) (const_int 24)))] |
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2014 ) |
0 | 2015 |
2016 ;; ---------------------------------------------------------------------- | |
2017 ;; PROLOGUE/EPILOGUE | |
2018 ;; ---------------------------------------------------------------------- | |
2019 (define_expand "prologue" | |
2020 [(const_int 0)] | |
2021 "" | |
67
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2022 { mn10300_expand_prologue (); DONE; } |
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2023 ) |
0 | 2024 |
2025 (define_expand "epilogue" | |
2026 [(return)] | |
2027 "" | |
67
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2028 { mn10300_expand_epilogue (); DONE; } |
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2029 ) |
0 | 2030 |
2031 (define_insn "return" | |
2032 [(return)] | |
67
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2033 "mn10300_can_use_rets_insn ()" |
0 | 2034 { |
67
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2035 /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger. */ |
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2036 if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ()) |
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2037 return "retf [],0"; |
0 | 2038 else |
67
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2039 return "rets"; |
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2040 }) |
0 | 2041 |
67
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2042 (define_insn "return_ret" |
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2043 [(return) |
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2044 (use (match_operand:SI 0 "const_int_operand" ""))] |
0 | 2045 "" |
2046 { | |
67
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2047 /* The RETF insn is up to 3 cycles faster than RET. */ |
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2048 fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file); |
111 | 2049 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs (NULL)); |
67
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2050 fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0])); |
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2051 return ""; |
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2052 }) |
0 | 2053 |
67
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2054 ;; This instruction matches one generated by mn10300_gen_multiple_store() |
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2055 (define_insn "store_movm" |
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2056 [(match_parallel 0 "mn10300_store_multiple_operation" |
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2057 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])] |
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2058 "" |
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2059 { |
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2060 fputs ("\tmovm ", asm_out_file); |
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|
2061 mn10300_print_reg_list (asm_out_file, |
111 | 2062 mn10300_store_multiple_regs (operands[0])); |
67
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|
2063 fprintf (asm_out_file, ",(sp)\n"); |
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|
2064 return ""; |
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|
2065 } |
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|
2066 ;; Assume that no more than 8 registers will be pushed. |
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2067 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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|
2068 (const_int 99) (const_int 88)))] |
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2069 ) |
0 | 2070 |
67
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|
2071 (define_expand "load_pic" |
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2072 [(const_int 0)] |
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|
2073 "flag_pic" |
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|
2074 { |
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|
2075 if (TARGET_AM33) |
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2076 emit_insn (gen_am33_load_pic (pic_offset_table_rtx)); |
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2077 else if (mn10300_frame_size () == 0) |
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2078 emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx)); |
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2079 else |
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2080 emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx)); |
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|
2081 DONE; |
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2082 }) |
0 | 2083 |
67
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|
2084 (define_insn "am33_load_pic" |
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2085 [(set (match_operand:SI 0 "register_operand" "=a") |
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|
2086 (unspec:SI [(const_int 0)] UNSPEC_GOT)) |
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2087 (clobber (reg:CC CC_REG))] |
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|
2088 "TARGET_AM33" |
0 | 2089 { |
67
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|
2090 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); |
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|
2091 return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0"; |
0 | 2092 } |
67
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|
2093 [(set_attr "timings" "33")] |
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|
2094 ) |
0 | 2095 |
67
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|
2096 ;; Load pic register with push/pop of stack. |
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|
2097 (define_insn "mn10300_load_pic0" |
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|
2098 [(set (match_operand:SI 0 "register_operand" "=a") |
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2099 (unspec:SI [(const_int 0)] UNSPEC_GOT)) |
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2100 (clobber (reg:SI MDR_REG)) |
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2101 (clobber (reg:CC CC_REG))] |
0 | 2102 "" |
2103 { | |
67
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|
2104 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); |
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2105 return ("add -4,sp\;" |
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2106 "calls .LPIC%=\n" |
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2107 ".LPIC%=:\;" |
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2108 "movm (sp),[%0]\;" |
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2109 "add %1-(.LPIC%=-.),%0"); |
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2110 } |
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2111 [(set_attr "timings" "88")] |
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2112 ) |
0 | 2113 |
67
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2114 ;; Load pic register re-using existing stack space. |
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2115 (define_insn "mn10300_load_pic1" |
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2116 [(set (match_operand:SI 0 "register_operand" "=a") |
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2117 (unspec:SI [(const_int 0)] UNSPEC_GOT)) |
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2118 (clobber (mem:SI (reg:SI SP_REG))) |
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2119 (clobber (reg:SI MDR_REG)) |
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2120 (clobber (reg:CC CC_REG))] |
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2121 "" |
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2122 { |
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2123 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); |
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2124 return ("calls .LPIC%=\n" |
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2125 ".LPIC%=:\;" |
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2126 "mov (sp),%0\;" |
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2127 "add %1-(.LPIC%=-.),%0"); |
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2128 } |
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2129 [(set_attr "timings" "66")] |
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2130 ) |
0 | 2131 |
67
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2132 ;; The mode on operand 3 has been deliberately omitted because it |
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2133 ;; can be either SI (for arithmetic operations) or QI (for shifts). |
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2134 (define_insn "liw" |
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2135 [(set (match_operand:SI 0 "register_operand" "=r") |
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2136 (unspec:SI [(match_dup 0) |
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2137 (match_operand 2 "liw_operand" "rO") |
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2138 (match_operand:SI 4 "const_int_operand" "")] |
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2139 UNSPEC_LIW)) |
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2140 (set (match_operand:SI 1 "register_operand" "=r") |
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2141 (unspec:SI [(match_dup 1) |
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2142 (match_operand 3 "liw_operand" "rO") |
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2143 (match_operand:SI 5 "const_int_operand" "")] |
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2144 UNSPEC_LIW))] |
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2145 "TARGET_ALLOW_LIW" |
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2146 "%W4_%W5 %2, %0, %3, %1" |
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2147 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2148 (const_int 13) (const_int 12)))] |
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2149 ) |
0 | 2150 |
67
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2151 ;; The mode on operand 1 has been deliberately omitted because it |
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2152 ;; can be either SI (for arithmetic operations) or QI (for shifts). |
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2153 (define_insn "cmp_liw" |
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2154 [(set (reg:CC CC_REG) |
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2155 (compare:CC (match_operand:SI 2 "register_operand" "r") |
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2156 (match_operand 3 "liw_operand" "rO"))) |
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2157 (set (match_operand:SI 0 "register_operand" "=r") |
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2158 (unspec:SI [(match_dup 0) |
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2159 (match_operand 1 "liw_operand" "rO") |
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2160 (match_operand:SI 4 "const_int_operand" "")] |
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2161 UNSPEC_LIW))] |
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2162 "TARGET_ALLOW_LIW" |
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2163 "cmp_%W4 %3, %2, %1, %0" |
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2164 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2165 (const_int 13) (const_int 12)))] |
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2166 ) |
0 | 2167 |
67
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2168 (define_insn "liw_cmp" |
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2169 [(set (match_operand:SI 0 "register_operand" "=r") |
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2170 (unspec:SI [(match_dup 0) |
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2171 (match_operand 1 "liw_operand" "rO") |
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2172 (match_operand:SI 4 "const_int_operand" "")] |
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|
2173 UNSPEC_LIW)) |
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2174 (set (reg:CC CC_REG) |
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2175 (compare:CC (match_operand:SI 2 "register_operand" "r") |
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2176 (match_operand 3 "liw_operand" "rO")))] |
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|
2177 "TARGET_ALLOW_LIW" |
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2178 "%W4_cmp %1, %0, %3, %2" |
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2179 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") |
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2180 (const_int 13) (const_int 12)))] |
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2181 ) |
111 | 2182 |
2183 ;; Note - in theory the doloop patterns could be used here to express | |
2184 ;; the SETLB and Lcc instructions. In practice this does not work because | |
2185 ;; the acceptable forms of the doloop patterns do not include UNSPECs | |
2186 ;; and without them gcc's basic block reordering code can duplicate the | |
2187 ;; doloop_end pattern, leading to bogus multiple decrements of the loop | |
2188 ;; counter. | |
2189 | |
2190 (define_insn "setlb" | |
2191 [(unspec [(const_int 0)] UNSPEC_SETLB)] | |
2192 "TARGET_AM33 && TARGET_ALLOW_SETLB" | |
2193 "setlb" | |
2194 ) | |
2195 | |
2196 (define_insn "Lcc" | |
2197 [(set (pc) | |
2198 (if_then_else (match_operator 0 "comparison_operator" | |
2199 [(reg:CC CC_REG) (const_int 0)]) | |
2200 (label_ref (match_operand 1 "" "")) | |
2201 (pc))) | |
2202 (unspec [(const_int 1)] UNSPEC_SETLB)] | |
2203 "TARGET_AM33 && TARGET_ALLOW_SETLB" | |
2204 "L%b0 # loop back to: %1" | |
2205 ) | |
2206 | |
2207 (define_insn "FLcc" | |
2208 [(set (pc) | |
2209 (if_then_else (match_operator 0 "comparison_operator" | |
2210 [(reg:CC_FLOAT CC_REG) (const_int 0)]) | |
2211 (label_ref (match_operand 1 "" "")) | |
2212 (pc))) | |
2213 (unspec [(const_int 2)] UNSPEC_SETLB)] | |
2214 "TARGET_AM33_2 && TARGET_ALLOW_SETLB" | |
2215 "FL%b0 # loop back to: %1" | |
2216 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 44) (const_int 11)))] | |
2217 ) |