Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/rs6000/power6.md @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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1 ;; Scheduling description for IBM POWER6 processor.
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77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
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2 ;; Copyright (C) 2006, 2007, 2009 Free Software Foundation, Inc.
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3 ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Sources:
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22
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23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine
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24 ;; (2 engines per chip). The chip can issue up to 5 internal ops
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25 ;; per cycle.
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26
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27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu")
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28
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29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu")
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30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu")
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31 (define_cpu_unit "bpu_power6" "power6bu")
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32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu")
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33
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34 (define_reservation "LS2_power6"
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35 "lsu1_power6+lsu2_power6")
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36
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37 (define_reservation "FPU_power6"
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38 "fpu1_power6|fpu2_power6")
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39
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40 (define_reservation "BRU_power6"
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41 "bpu_power6")
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42
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43 (define_reservation "LSU_power6"
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44 "lsu1_power6|lsu2_power6")
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45
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46 (define_reservation "LSF_power6"
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47 "(lsu1_power6+fpu1_power6)\
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48 |(lsu1_power6+fpu2_power6)\
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49 |(lsu2_power6+fpu1_power6)\
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50 |(lsu2_power6+fpu2_power6)")
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51
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52 (define_reservation "LX2_power6"
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53 "(iu1_power6+iu2_power6+lsu1_power6)\
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54 |(iu1_power6+iu2_power6+lsu2_power6)")
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55
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56 (define_reservation "FX2_power6"
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57 "iu1_power6+iu2_power6")
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58
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59 (define_reservation "X2F_power6"
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60 "(iu1_power6+iu2_power6+fpu1_power6)\
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61 |(iu1_power6+iu2_power6+fpu2_power6)")
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62
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63 (define_reservation "BX2_power6"
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64 "iu1_power6+iu2_power6+bpu_power6")
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65
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66 (define_reservation "LSX_power6"
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67 "(iu1_power6+lsu1_power6)\
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68 |(iu1_power6+lsu2_power6)\
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69 |(iu2_power6+lsu1_power6)\
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70 |(iu2_power6+lsu2_power6)")
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71
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72 (define_reservation "FXU_power6"
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73 "iu1_power6|iu2_power6")
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74
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75 (define_reservation "XLF_power6"
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76 "(iu1_power6+lsu1_power6+fpu1_power6)\
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77 |(iu1_power6+lsu1_power6+fpu2_power6)\
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78 |(iu1_power6+lsu2_power6+fpu1_power6)\
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79 |(iu1_power6+lsu2_power6+fpu2_power6)\
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80 |(iu2_power6+lsu1_power6+fpu1_power6)\
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81 |(iu2_power6+lsu1_power6+fpu2_power6)\
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82 |(iu2_power6+lsu2_power6+fpu1_power6)\
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83 |(iu2_power6+lsu2_power6+fpu2_power6)")
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84
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85 (define_reservation "BRX_power6"
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86 "(bpu_power6+iu1_power6)\
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87 |(bpu_power6+iu2_power6)")
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88
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89 ; Load/store
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90
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91 ; The default for a value written by a fixed point load
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92 ; that is read/written by a subsequent fixed point op.
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93 (define_insn_reservation "power6-load" 2 ; fx
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94 (and (eq_attr "type" "load")
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95 (eq_attr "cpu" "power6"))
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96 "LSU_power6")
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97
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98 ; define the bypass for the case where the value written
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99 ; by a fixed point load is used as the source value on
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100 ; a store.
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101 (define_bypass 1 "power6-load,\
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102 power6-load-update,\
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103 power6-load-update-indexed"
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104 "power6-store,\
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105 power6-store-update,\
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106 power6-store-update-indexed,\
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107 power6-fpstore,\
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108 power6-fpstore-update"
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109 "store_data_bypass_p")
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110
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111 (define_insn_reservation "power6-load-ext" 4 ; fx
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112 (and (eq_attr "type" "load_ext")
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113 (eq_attr "cpu" "power6"))
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114 "LSU_power6")
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115
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116 ; define the bypass for the case where the value written
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117 ; by a fixed point load ext is used as the source value on
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118 ; a store.
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119 (define_bypass 1 "power6-load-ext,\
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120 power6-load-ext-update,\
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121 power6-load-ext-update-indexed"
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122 "power6-store,\
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123 power6-store-update,\
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124 power6-store-update-indexed,\
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125 power6-fpstore,\
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126 power6-fpstore-update"
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127 "store_data_bypass_p")
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128
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129 (define_insn_reservation "power6-load-update" 2 ; fx
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130 (and (eq_attr "type" "load_u")
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131 (eq_attr "cpu" "power6"))
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132 "LSX_power6")
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133
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134 (define_insn_reservation "power6-load-update-indexed" 2 ; fx
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135 (and (eq_attr "type" "load_ux")
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136 (eq_attr "cpu" "power6"))
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137 "LSX_power6")
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138
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139 (define_insn_reservation "power6-load-ext-update" 4 ; fx
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140 (and (eq_attr "type" "load_ext_u")
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141 (eq_attr "cpu" "power6"))
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142 "LSX_power6")
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143
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 (and (eq_attr "type" "load_ext_ux")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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147 "LSX_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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148
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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149 (define_insn_reservation "power6-fpload" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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150 (and (eq_attr "type" "fpload")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 "LSU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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153
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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154 (define_insn_reservation "power6-fpload-update" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 (and (eq_attr "type" "fpload_u,fpload_ux")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 "LSX_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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158
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 (define_insn_reservation "power6-store" 14
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 (and (eq_attr "type" "store")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 "LSU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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163
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 (define_insn_reservation "power6-store-update" 14
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 (and (eq_attr "type" "store_u")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 "LSX_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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168
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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169 (define_insn_reservation "power6-store-update-indexed" 14
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 (and (eq_attr "type" "store_ux")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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171 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 "LX2_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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173
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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174 (define_insn_reservation "power6-fpstore" 14
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 (and (eq_attr "type" "fpstore")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 "LSF_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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178
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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179 (define_insn_reservation "power6-fpstore-update" 14
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 (and (eq_attr "type" "fpstore_u,fpstore_ux")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 "XLF_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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183
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 (define_insn_reservation "power6-larx" 3
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 (and (eq_attr "type" "load_l")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 "LS2_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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188
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 (define_insn_reservation "power6-stcx" 10 ; best case
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 (and (eq_attr "type" "store_c")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 "LSX_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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193
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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194 (define_insn_reservation "power6-sync" 11 ; N/A
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 (and (eq_attr "type" "sync")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 "LSU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
198
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 (define_insn_reservation "power6-integer" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
200 (and (eq_attr "type" "integer")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
201 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
204 (define_insn_reservation "power6-isel" 1
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205 (and (eq_attr "type" "isel")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
206 (eq_attr "cpu" "power6"))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
207 "FXU_power6")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
208
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 (define_insn_reservation "power6-exts" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 (and (eq_attr "type" "exts")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
213
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 (define_insn_reservation "power6-shift" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 (and (eq_attr "type" "shift")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
217 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
218
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 (define_insn_reservation "power6-insert" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
220 (and (eq_attr "type" "insert_word")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
221 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
222 "FX2_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
223
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
224 (define_insn_reservation "power6-insert-dword" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
225 (and (eq_attr "type" "insert_dword")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
226 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
227 "FX2_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
228
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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229 ; define the bypass for the case where the value written
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 ; by a fixed point op is used as the source value on a
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
231 ; store.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 (define_bypass 1 "power6-integer,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
233 power6-exts,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 power6-shift,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
235 power6-insert,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 power6-insert-dword"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
237 "power6-store,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 power6-store-update,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
239 power6-store-update-indexed,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 power6-fpstore,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 power6-fpstore-update"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 "store_data_bypass_p")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
243
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 (define_insn_reservation "power6-cntlz" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 (and (eq_attr "type" "cntlz")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
248
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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249 (define_bypass 1 "power6-cntlz"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 "power6-store,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 power6-store-update,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 power6-store-update-indexed,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 power6-fpstore,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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254 power6-fpstore-update"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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255 "store_data_bypass_p")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
256
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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257 (define_insn_reservation "power6-var-rotate" 4
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 (and (eq_attr "type" "var_shift_rotate")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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260 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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261
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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262 (define_insn_reservation "power6-trap" 1 ; N/A
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 (and (eq_attr "type" "trap")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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265 "BRX_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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266
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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267 (define_insn_reservation "power6-two" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 (and (eq_attr "type" "two")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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269 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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270 "(iu1_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 |(iu1_power6+iu2_power6,nothing)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
272 |(iu1_power6,iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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273 |(iu2_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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274 |(iu2_power6,iu2_power6)")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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275
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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276 (define_insn_reservation "power6-three" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
277 (and (eq_attr "type" "three")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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278 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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279 "(iu1_power6,iu1_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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280 |(iu1_power6,iu1_power6,iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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281 |(iu1_power6,iu2_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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282 |(iu1_power6,iu2_power6,iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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283 |(iu2_power6,iu1_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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284 |(iu2_power6,iu1_power6,iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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285 |(iu2_power6,iu2_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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286 |(iu2_power6,iu2_power6,iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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287 |(iu1_power6+iu2_power6,iu1_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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288 |(iu1_power6+iu2_power6,iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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289 |(iu1_power6,iu1_power6+iu2_power6)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 |(iu2_power6,iu1_power6+iu2_power6)")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
291
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 (define_insn_reservation "power6-cmp" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 (and (eq_attr "type" "cmp")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
296
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 (define_insn_reservation "power6-compare" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
298 (and (eq_attr "type" "compare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
300 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
301
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
302 (define_insn_reservation "power6-fast-compare" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 (and (eq_attr "type" "fast_compare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
306
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 ; define the bypass for the case where the value written
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 ; by a fixed point rec form op is used as the source value
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 ; on a store.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
310 (define_bypass 1 "power6-compare,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 power6-fast-compare"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 "power6-store,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 power6-store-update,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 power6-store-update-indexed,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
315 power6-fpstore,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 power6-fpstore-update"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 "store_data_bypass_p")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
318
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 (define_insn_reservation "power6-delayed-compare" 2 ; N/A
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
320 (and (eq_attr "type" "delayed_compare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
323
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 (define_insn_reservation "power6-var-delayed-compare" 4
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 (and (eq_attr "type" "var_delayed_compare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
327 "FXU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
328
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 (define_insn_reservation "power6-lmul-cmp" 16
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 (and (eq_attr "type" "lmul_compare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
331 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
332 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
334
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 (define_insn_reservation "power6-imul-cmp" 16
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
336 (and (eq_attr "type" "imul_compare")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
337 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
338 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
339 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
340
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
341 (define_insn_reservation "power6-lmul" 16
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
342 (and (eq_attr "type" "lmul")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
343 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
344 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
346
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
347 (define_insn_reservation "power6-imul" 16
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
348 (and (eq_attr "type" "imul")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
351 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
352
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
353 (define_insn_reservation "power6-imul3" 16
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
354 (and (eq_attr "type" "imul2,imul3")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
355 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
356 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
357 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
358
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
359 (define_bypass 9 "power6-imul,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
360 power6-lmul,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
361 power6-imul-cmp,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 power6-lmul-cmp,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 power6-imul3"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
364 "power6-store,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
365 power6-store-update,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
366 power6-store-update-indexed,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 power6-fpstore,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
368 power6-fpstore-update"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
369 "store_data_bypass_p")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
370
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
371 (define_insn_reservation "power6-idiv" 44
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
372 (and (eq_attr "type" "idiv")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
373 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
374 "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)");
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
376
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 ; The latency for this bypass is yet to be defined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 ;(define_bypass ? "power6-idiv"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 ; "power6-store,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
380 ; power6-store-update,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 ; power6-store-update-indexed,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 ; power6-fpstore,\
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
383 ; power6-fpstore-update"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
384 ; "store_data_bypass_p")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
385
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
386 (define_insn_reservation "power6-ldiv" 56
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
387 (and (eq_attr "type" "ldiv")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
388 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)");
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
391
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
392 ; The latency for this bypass is yet to be defined
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
393 ;(define_bypass ? "power6-ldiv"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 ; "power6-store,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 ; power6-store-update,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
396 ; power6-store-update-indexed,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 ; power6-fpstore,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 ; power6-fpstore-update"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 ; "store_data_bypass_p")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
400
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
401 (define_insn_reservation "power6-mtjmpr" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 (and (eq_attr "type" "mtjmpr,mfjmpr")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 "BX2_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
405
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 (define_bypass 5 "power6-mtjmpr" "power6-branch")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
407
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 (define_insn_reservation "power6-branch" 2
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
409 (and (eq_attr "type" "jmpreg,branch")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 "BRU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
412
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 (define_bypass 5 "power6-branch" "power6-mtjmpr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
414
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 (define_insn_reservation "power6-crlogical" 3
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 (and (eq_attr "type" "cr_logical")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
417 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
418 "BRU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
419
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 (define_bypass 3 "power6-crlogical" "power6-branch")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
421
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 (define_insn_reservation "power6-delayedcr" 3
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 (and (eq_attr "type" "delayed_cr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 "BRU_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 (define_insn_reservation "power6-mfcr" 6 ; N/A
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 (and (eq_attr "type" "mfcr")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 (eq_attr "cpu" "power6"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
430 "BX2_power6")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
431
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 ; mfcrf (1 field)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
433 (define_insn_reservation "power6-mfcrf" 3 ; N/A
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 (and (eq_attr "type" "mfcrf")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
435 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 "BX2_power6") ;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
437
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 ; mtcrf (1 field)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 (define_insn_reservation "power6-mtcr" 4 ; N/A
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 (and (eq_attr "type" "mtcr")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 "BX2_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
443
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 (define_bypass 9 "power6-mtcr" "power6-branch")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
445
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 (define_insn_reservation "power6-fp" 6
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 (and (eq_attr "type" "fp,dmul")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 ; Any fp instruction that updates a CR has a latency
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 ; of 6 to a dependent branch
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 (define_bypass 6 "power6-fp" "power6-branch")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
454
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
455 (define_bypass 1 "power6-fp"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 "power6-fpstore,power6-fpstore-update"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 "store_data_bypass_p")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
458
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
459 (define_insn_reservation "power6-fpcompare" 8
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
460 (and (eq_attr "type" "fpcompare")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
461 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
462 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
463
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
464 (define_bypass 12 "power6-fpcompare"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
465 "power6-branch,power6-crlogical")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
466
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 (define_insn_reservation "power6-sdiv" 26
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 (and (eq_attr "type" "sdiv")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
471
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 (define_insn_reservation "power6-ddiv" 32
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
473 (and (eq_attr "type" "ddiv")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
474 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
475 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
476
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
477 (define_insn_reservation "power6-sqrt" 30
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
478 (and (eq_attr "type" "ssqrt")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
479 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
480 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
481
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 (define_insn_reservation "power6-dsqrt" 42
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 (and (eq_attr "type" "dsqrt")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
484 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
485 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
486
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
487 (define_insn_reservation "power6-isync" 2 ; N/A
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
488 (and (eq_attr "type" "isync")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 "FXU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
491
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
492 (define_insn_reservation "power6-vecload" 1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 (and (eq_attr "type" "vecload")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 "LSU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
496
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 (define_insn_reservation "power6-vecstore" 1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
498 (and (eq_attr "type" "vecstore")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
499 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
500 "LSF_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
501
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
502 (define_insn_reservation "power6-vecsimple" 3
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
503 (and (eq_attr "type" "vecsimple")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
506
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
507 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 power6-vecperm")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
509
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
510 (define_bypass 5 "power6-vecsimple" "power6-vecfloat")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
511
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
512 (define_bypass 4 "power6-vecsimple" "power6-vecstore" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
513
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
514 (define_insn_reservation "power6-veccmp" 1
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
515 (and (eq_attr "type" "veccmp")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
516 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
517 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
518
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
519 (define_bypass 10 "power6-veccmp" "power6-branch")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
520
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
521 (define_insn_reservation "power6-vecfloat" 7
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
522 (and (eq_attr "type" "vecfloat")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
523 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
524 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
525
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
526 (define_bypass 10 "power6-vecfloat" "power6-vecsimple")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
527
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
528 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
529 power6-vecperm")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
530
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
531 (define_bypass 9 "power6-vecfloat" "power6-vecstore" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
532
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
533 (define_insn_reservation "power6-veccomplex" 7
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
534 (and (eq_attr "type" "vecsimple")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
535 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
536 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
537
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
538 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
539 power6-vecfloat" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
540
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
541 (define_bypass 9 "power6-veccomplex" "power6-vecperm" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
542
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
543 (define_bypass 8 "power6-veccomplex" "power6-vecstore" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
544
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
545 (define_insn_reservation "power6-vecperm" 4
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
546 (and (eq_attr "type" "vecperm")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
547 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
548 "FPU_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
549
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
550 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
551 power6-vecfloat" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
552
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
553 (define_bypass 6 "power6-vecperm" "power6-veccomplex" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
554
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
555 (define_bypass 5 "power6-vecperm" "power6-vecstore" )
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
556
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
557 (define_insn_reservation "power6-mftgpr" 8
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
558 (and (eq_attr "type" "mftgpr")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
559 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
560 "X2F_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
561
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
562 (define_insn_reservation "power6-mffgpr" 14
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
563 (and (eq_attr "type" "mffgpr")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
564 (eq_attr "cpu" "power6"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
565 "LX2_power6")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
566
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
567 (define_bypass 4 "power6-mftgpr" "power6-imul,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
568 power6-lmul,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
569 power6-imul-cmp,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
570 power6-lmul-cmp,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
571 power6-imul3,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
572 power6-idiv,\
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
573 power6-ldiv" )