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1 ;; ARM 1020E & ARM 1022E Pipeline Description
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2 ;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
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3 ;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; ARM1020E Technical Reference Manual, Copyright (c) 2003 ARM
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23 ;; Limited.
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24 ;;
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25
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26 ;; This automaton provides a pipeline description for the ARM
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27 ;; 1020E core.
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28 ;;
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29 ;; The model given here assumes that the condition for all conditional
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30 ;; instructions is "true", i.e., that all of the instructions are
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31 ;; actually executed.
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32
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33 (define_automaton "arm1020e")
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34
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35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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36 ;; Pipelines
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37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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38
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39 ;; There are two pipelines:
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40 ;;
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41 ;; - An Arithmetic Logic Unit (ALU) pipeline.
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42 ;;
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43 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
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44 ;; write stages. We only need to model the execute, memory and write
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45 ;; stages.
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46 ;;
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47 ;; - A Load-Store Unit (LSU) pipeline.
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48 ;;
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49 ;; The LSU pipeline has decode, execute, memory, and write stages.
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50 ;; We only model the execute, memory and write stages.
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51
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52 (define_cpu_unit "1020a_e,1020a_m,1020a_w" "arm1020e")
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53 (define_cpu_unit "1020l_e,1020l_m,1020l_w" "arm1020e")
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54
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55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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56 ;; ALU Instructions
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57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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58
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59 ;; ALU instructions require three cycles to execute, and use the ALU
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60 ;; pipeline in each of the three stages. The results are available
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61 ;; after the execute stage stage has finished.
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62 ;;
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63 ;; If the destination register is the PC, the pipelines are stalled
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64 ;; for several cycles. That case is not modeled here.
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65
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66 ;; ALU operations with no shifted operand
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67 (define_insn_reservation "1020alu_op" 1
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68 (and (eq_attr "tune" "arm1020e,arm1022e")
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69 (eq_attr "type" "alu"))
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70 "1020a_e,1020a_m,1020a_w")
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71
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72 ;; ALU operations with a shift-by-constant operand
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73 (define_insn_reservation "1020alu_shift_op" 1
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74 (and (eq_attr "tune" "arm1020e,arm1022e")
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75 (eq_attr "type" "alu_shift"))
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76 "1020a_e,1020a_m,1020a_w")
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77
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78 ;; ALU operations with a shift-by-register operand
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79 ;; These really stall in the decoder, in order to read
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80 ;; the shift value in a second cycle. Pretend we take two cycles in
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81 ;; the execute stage.
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82 (define_insn_reservation "1020alu_shift_reg_op" 2
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83 (and (eq_attr "tune" "arm1020e,arm1022e")
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84 (eq_attr "type" "alu_shift_reg"))
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85 "1020a_e*2,1020a_m,1020a_w")
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86
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87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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88 ;; Multiplication Instructions
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89 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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90
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91 ;; Multiplication instructions loop in the execute stage until the
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92 ;; instruction has been passed through the multiplier array enough
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93 ;; times.
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94
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95 ;; The result of the "smul" and "smulw" instructions is not available
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96 ;; until after the memory stage.
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97 (define_insn_reservation "1020mult1" 2
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98 (and (eq_attr "tune" "arm1020e,arm1022e")
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99 (eq_attr "insn" "smulxy,smulwy"))
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100 "1020a_e,1020a_m,1020a_w")
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101
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102 ;; The "smlaxy" and "smlawx" instructions require two iterations through
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103 ;; the execute stage; the result is available immediately following
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104 ;; the execute stage.
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105 (define_insn_reservation "1020mult2" 2
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106 (and (eq_attr "tune" "arm1020e,arm1022e")
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107 (eq_attr "insn" "smlaxy,smlalxy,smlawx"))
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108 "1020a_e*2,1020a_m,1020a_w")
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109
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110 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
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111 ;; through the execute stage; the result is not available until after
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112 ;; the memory stage.
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113 (define_insn_reservation "1020mult3" 3
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114 (and (eq_attr "tune" "arm1020e,arm1022e")
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115 (eq_attr "insn" "smlalxy,mul,mla"))
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116 "1020a_e*2,1020a_m,1020a_w")
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117
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118 ;; The "muls" and "mlas" instructions loop in the execute stage for
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119 ;; four iterations in order to set the flags. The value result is
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120 ;; available after three iterations.
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121 (define_insn_reservation "1020mult4" 3
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122 (and (eq_attr "tune" "arm1020e,arm1022e")
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123 (eq_attr "insn" "muls,mlas"))
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124 "1020a_e*4,1020a_m,1020a_w")
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125
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126 ;; Long multiply instructions that produce two registers of
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127 ;; output (such as umull) make their results available in two cycles;
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128 ;; the least significant word is available before the most significant
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129 ;; word. That fact is not modeled; instead, the instructions are
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130 ;; described.as if the entire result was available at the end of the
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131 ;; cycle in which both words are available.
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132
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133 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
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134 ;; three iterations through the execute cycle, and make their results
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135 ;; available after the memory cycle.
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136 (define_insn_reservation "1020mult5" 4
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137 (and (eq_attr "tune" "arm1020e,arm1022e")
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138 (eq_attr "insn" "umull,umlal,smull,smlal"))
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139 "1020a_e*3,1020a_m,1020a_w")
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140
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141 ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
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142 ;; the execute stage for five iterations in order to set the flags.
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143 ;; The value result is available after four iterations.
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144 (define_insn_reservation "1020mult6" 4
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145 (and (eq_attr "tune" "arm1020e,arm1022e")
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146 (eq_attr "insn" "umulls,umlals,smulls,smlals"))
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147 "1020a_e*5,1020a_m,1020a_w")
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148
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149 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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150 ;; Load/Store Instructions
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151 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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152
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153 ;; The models for load/store instructions do not accurately describe
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154 ;; the difference between operations with a base register writeback
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155 ;; (such as "ldm!"). These models assume that all memory references
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156 ;; hit in dcache.
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157
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158 ;; LSU instructions require six cycles to execute. They use the ALU
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159 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
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160 ;; three through six.
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161 ;; Loads and stores which use a scaled register offset or scaled
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162 ;; register pre-indexed addressing mode take three cycles EXCEPT for
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163 ;; those that are base + offset with LSL of 0 or 2, or base - offset
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164 ;; with LSL of zero. The remainder take 1 cycle to execute.
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165 ;; For 4byte loads there is a bypass from the load stage
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166
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167 (define_insn_reservation "1020load1_op" 2
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168 (and (eq_attr "tune" "arm1020e,arm1022e")
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169 (eq_attr "type" "load_byte,load1"))
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170 "1020a_e+1020l_e,1020l_m,1020l_w")
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171
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172 (define_insn_reservation "1020store1_op" 0
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173 (and (eq_attr "tune" "arm1020e,arm1022e")
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174 (eq_attr "type" "store1"))
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175 "1020a_e+1020l_e,1020l_m,1020l_w")
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176
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177 ;; A load's result can be stored by an immediately following store
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178 (define_bypass 1 "1020load1_op" "1020store1_op" "arm_no_early_store_addr_dep")
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179
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180 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
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181 ;; registers have been processed.
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182 ;;
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183 ;; The time it takes to load the data depends on whether or not the
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184 ;; base address is 64-bit aligned; if it is not, an additional cycle
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185 ;; is required. This model assumes that the address is always 64-bit
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186 ;; aligned. Because the processor can load two registers per cycle,
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187 ;; that assumption means that we use the same instruction reservations
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188 ;; for loading 2k and 2k - 1 registers.
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189 ;;
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190 ;; The ALU pipeline is decoupled after the first cycle unless there is
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191 ;; a register dependency; the dependency is cleared as soon as the LDM/STM
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192 ;; has dealt with the corresponding register. So for example,
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193 ;; stmia sp, {r0-r3}
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194 ;; add r0, r0, #4
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195 ;; will have one fewer stalls than
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196 ;; stmia sp, {r0-r3}
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197 ;; add r3, r3, #4
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198 ;;
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199 ;; As with ALU operations, if one of the destination registers is the
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200 ;; PC, there are additional stalls; that is not modeled.
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201
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202 (define_insn_reservation "1020load2_op" 2
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203 (and (eq_attr "tune" "arm1020e,arm1022e")
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204 (eq_attr "type" "load2"))
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205 "1020a_e+1020l_e,1020l_m,1020l_w")
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206
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207 (define_insn_reservation "1020store2_op" 0
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208 (and (eq_attr "tune" "arm1020e,arm1022e")
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209 (eq_attr "type" "store2"))
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210 "1020a_e+1020l_e,1020l_m,1020l_w")
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211
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212 (define_insn_reservation "1020load34_op" 3
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213 (and (eq_attr "tune" "arm1020e,arm1022e")
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214 (eq_attr "type" "load3,load4"))
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215 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
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216
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217 (define_insn_reservation "1020store34_op" 0
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218 (and (eq_attr "tune" "arm1020e,arm1022e")
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219 (eq_attr "type" "store3,store4"))
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220 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
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221
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222 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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223 ;; Branch and Call Instructions
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224 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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225
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226 ;; Branch instructions are difficult to model accurately. The ARM
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227 ;; core can predict most branches. If the branch is predicted
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228 ;; correctly, and predicted early enough, the branch can be completely
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229 ;; eliminated from the instruction stream. Some branches can
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230 ;; therefore appear to require zero cycles to execute. We assume that
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231 ;; all branches are predicted correctly, and that the latency is
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232 ;; therefore the minimum value.
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233
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234 (define_insn_reservation "1020branch_op" 0
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235 (and (eq_attr "tune" "arm1020e,arm1022e")
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236 (eq_attr "type" "branch"))
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237 "1020a_e")
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238
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239 ;; The latency for a call is not predictable. Therefore, we use 32 as
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240 ;; roughly equivalent to positive infinity.
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241
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242 (define_insn_reservation "1020call_op" 32
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243 (and (eq_attr "tune" "arm1020e,arm1022e")
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244 (eq_attr "type" "call"))
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245 "1020a_e*32")
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246
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247 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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248 ;; VFP
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249 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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250
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251 (define_cpu_unit "v10_fmac" "arm1020e")
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252
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253 (define_cpu_unit "v10_ds" "arm1020e")
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254
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255 (define_cpu_unit "v10_fmstat" "arm1020e")
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256
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257 (define_cpu_unit "v10_ls1,v10_ls2,v10_ls3" "arm1020e")
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258
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259 ;; fmstat is a serializing instruction. It will stall the core until
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260 ;; the mac and ds units have completed.
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261 (exclusion_set "v10_fmac,v10_ds" "v10_fmstat")
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262
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263 (define_attr "vfp10" "yes,no"
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264 (const (if_then_else (and (eq_attr "tune" "arm1020e,arm1022e")
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265 (eq_attr "fpu" "vfp"))
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266 (const_string "yes") (const_string "no"))))
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267
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268 ;; Note, no instruction can issue to the VFP if the core is stalled in the
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269 ;; first execute state. We model this by using 1020a_e in the first cycle.
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270 (define_insn_reservation "v10_ffarith" 5
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271 (and (eq_attr "vfp10" "yes")
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272 (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
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273 "1020a_e+v10_fmac")
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274
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275 (define_insn_reservation "v10_farith" 5
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276 (and (eq_attr "vfp10" "yes")
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277 (eq_attr "type" "faddd,fadds"))
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278 "1020a_e+v10_fmac")
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279
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280 (define_insn_reservation "v10_cvt" 5
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281 (and (eq_attr "vfp10" "yes")
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282 (eq_attr "type" "f_cvt"))
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283 "1020a_e+v10_fmac")
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284
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285 (define_insn_reservation "v10_fmul" 6
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286 (and (eq_attr "vfp10" "yes")
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287 (eq_attr "type" "fmuls,fmacs,fmuld,fmacd"))
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288 "1020a_e+v10_fmac*2")
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289
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290 (define_insn_reservation "v10_fdivs" 18
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291 (and (eq_attr "vfp10" "yes")
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292 (eq_attr "type" "fdivs"))
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293 "1020a_e+v10_ds*14")
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294
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295 (define_insn_reservation "v10_fdivd" 32
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296 (and (eq_attr "vfp10" "yes")
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297 (eq_attr "type" "fdivd"))
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298 "1020a_e+v10_fmac+v10_ds*28")
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299
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300 (define_insn_reservation "v10_floads" 4
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301 (and (eq_attr "vfp10" "yes")
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302 (eq_attr "type" "f_loads"))
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303 "1020a_e+1020l_e+v10_ls1,v10_ls2")
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304
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305 ;; We model a load of a double as needing all the vfp ls* stage in cycle 1.
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306 ;; This gives the correct mix between single-and double loads where a flds
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307 ;; followed by and fldd will stall for one cycle, but two back-to-back fldd
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308 ;; insns stall for two cycles.
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309 (define_insn_reservation "v10_floadd" 5
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310 (and (eq_attr "vfp10" "yes")
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311 (eq_attr "type" "f_loadd"))
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312 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
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313
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314 ;; Moves to/from arm regs also use the load/store pipeline.
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315
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316 (define_insn_reservation "v10_c2v" 4
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317 (and (eq_attr "vfp10" "yes")
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318 (eq_attr "type" "r_2_f"))
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319 "1020a_e+1020l_e+v10_ls1,v10_ls2")
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320
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321 (define_insn_reservation "v10_fstores" 1
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322 (and (eq_attr "vfp10" "yes")
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323 (eq_attr "type" "f_stores"))
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324 "1020a_e+1020l_e+v10_ls1,v10_ls2")
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325
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326 (define_insn_reservation "v10_fstored" 1
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327 (and (eq_attr "vfp10" "yes")
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328 (eq_attr "type" "f_stored"))
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329 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
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330
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331 (define_insn_reservation "v10_v2c" 1
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332 (and (eq_attr "vfp10" "yes")
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333 (eq_attr "type" "f_2_r"))
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334 "1020a_e+1020l_e,1020l_m,1020l_w")
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335
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336 (define_insn_reservation "v10_to_cpsr" 2
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337 (and (eq_attr "vfp10" "yes")
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338 (eq_attr "type" "f_flag"))
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339 "1020a_e+v10_fmstat,1020a_e+1020l_e,1020l_m,1020l_w")
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340
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341 ;; VFP bypasses
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342
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343 ;; There are bypasses for most operations other than store
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344
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345 (define_bypass 3
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346 "v10_c2v,v10_floads"
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347 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd,v10_cvt")
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348
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349 (define_bypass 4
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350 "v10_floadd"
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351 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
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352
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353 ;; Arithmetic to other arithmetic saves a cycle due to forwarding
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354 (define_bypass 4
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355 "v10_ffarith,v10_farith"
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356 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
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357
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358 (define_bypass 5
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359 "v10_fmul"
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360 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
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361
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362 (define_bypass 17
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363 "v10_fdivs"
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364 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
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365
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366 (define_bypass 31
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367 "v10_fdivd"
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368 "v10_ffarith,v10_farith,v10_fmul,v10_fdivs,v10_fdivd")
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369
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370 ;; VFP anti-dependencies.
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371
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372 ;; There is one anti-dependence in the following case (not yet modelled):
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373 ;; - After a store: one extra cycle for both fsts and fstd
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374 ;; Note, back-to-back fstd instructions will overload the load/store datapath
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375 ;; causing a two-cycle stall.
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