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1 (* Emission of the core of the Cortex-A8 NEON scheduling description.
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2 Copyright (C) 2007 Free Software Foundation, Inc.
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3 Contributed by CodeSourcery.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it under
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8 the terms of the GNU General Public License as published by the Free
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9 Software Foundation; either version 3, or (at your option) any later
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10 version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>.
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20 *)
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21
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22 (* This scheduling description generator works as follows.
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23 - Each group of instructions has source and destination requirements
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24 specified. The source requirements may be specified using
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25 Source (the stage at which all source operands not otherwise
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26 described are read), Source_m (the stage at which Rm operands are
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27 read), Source_n (likewise for Rn) and Source_d (likewise for Rd).
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28 - For each group of instructions the earliest stage where a source
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29 operand may be required is calculated.
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30 - Each group of instructions is selected in turn as a producer.
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31 The latencies between this group and every other group are then
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32 calculated, yielding up to four values for each combination:
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33 1. Producer -> consumer Rn latency
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34 2. Producer -> consumer Rm latency
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35 3. Producer -> consumer Rd (as a source) latency
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36 4. Producer -> consumer worst-case latency.
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37 Value 4 is calculated from the destination availability requirements
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38 of the consumer and the earliest source availability requirements
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39 of the producer.
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40 - The largest Value 4 calculated for the current producer is the
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41 worse-case latency, L, for that instruction group. This value is written
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42 out in a define_insn_reservation for the producer group.
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43 - For each producer and consumer pair, the latencies calculated above
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44 are collated. The average (of up to four values) is calculated and
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45 if this average is different from the worst-case latency, an
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46 unguarded define_bypass construction is issued for that pair.
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47 (For each pair only one define_bypass construction will be emitted,
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48 and at present we do not emit specific guards.)
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49 *)
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50
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51 open Utils
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52
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53 let n1 = 1 and n2 = 2 and n3 = 3 and n4 = 4 and n5 = 5 and n6 = 6
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54 and n7 = 7 and n8 = 8 and n9 = 9
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55
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56 type availability = Source of int
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57 | Source_n of int
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58 | Source_m of int
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59 | Source_d of int
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60 | Dest of int
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61 | Dest_n_after of int * int
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62
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63 type guard = Guard_none | Guard_only_m | Guard_only_n | Guard_only_d
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64
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65 (* Reservation behaviors. All but the last row here correspond to one
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66 pipeline each. Each constructor will correspond to one
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67 define_reservation. *)
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68 type reservation =
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69 Mul | Mul_2cycle | Mul_4cycle
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70 | Shift | Shift_2cycle
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71 | ALU | ALU_2cycle
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72 | Fmul | Fmul_2cycle
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73 | Fadd | Fadd_2cycle
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74 (* | VFP *)
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75 | Permute of int
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76 | Ls of int
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77 | Fmul_then_fadd | Fmul_then_fadd_2
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78
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79 (* This table must be kept as short as possible by conflating
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80 entries with the same availability behavior.
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81
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82 First components: instruction group names
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83 Second components: availability requirements, in the order in which
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84 they should appear in the comments in the .md file.
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85 Third components: reservation info
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86 *)
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87 let availability_table = [
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88 (* NEON integer ALU instructions. *)
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89 (* vbit vbif vbsl vorr vbic vnot vcls vclz vcnt vadd vand vorr
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90 veor vbic vorn ddd qqq *)
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91 "neon_int_1", [Source n2; Dest n3], ALU;
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92 (* vadd vsub qqd vsub ddd qqq *)
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93 "neon_int_2", [Source_m n1; Source_n n2; Dest n3], ALU;
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94 (* vsum vneg dd qq vadd vsub qdd *)
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95 "neon_int_3", [Source n1; Dest n3], ALU;
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96 (* vabs vceqz vcgez vcbtz vclez vcltz vadh vradh vsbh vrsbh dqq *)
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97 (* vhadd vrhadd vqadd vtst ddd qqq *)
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98 "neon_int_4", [Source n2; Dest n4], ALU;
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99 (* vabd qdd vhsub vqsub vabd vceq vcge vcgt vmax vmin vfmx vfmn ddd ddd *)
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100 "neon_int_5", [Source_m n1; Source_n n2; Dest n4], ALU;
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101 (* vqneg vqabs dd qq *)
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102 "neon_vqneg_vqabs", [Source n1; Dest n4], ALU;
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103 (* vmov vmvn *)
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104 "neon_vmov", [Dest n3], ALU;
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105 (* vaba *)
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106 "neon_vaba", [Source_n n2; Source_m n1; Source_d n3; Dest n6], ALU;
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107 "neon_vaba_qqq",
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108 [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], ALU_2cycle;
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109 (* vsma *)
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110 "neon_vsma", [Source_m n1; Source_d n3; Dest n6], ALU;
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111
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112 (* NEON integer multiply instructions. *)
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113 (* vmul, vqdmlh, vqrdmlh *)
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114 (* vmul, vqdmul, qdd 16/8 long 32/16 long *)
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115 "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long", [Source n2; Dest n6], Mul;
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116 "neon_mul_qqq_8_16_32_ddd_32", [Source n2; Dest_n_after (1, n6)], Mul_2cycle;
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117 (* vmul, vqdmul again *)
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118 "neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar",
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119 [Source_n n2; Source_m n1; Dest_n_after (1, n6)], Mul_2cycle;
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120 (* vmla, vmls *)
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121 "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long",
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122 [Source_n n2; Source_m n2; Source_d n3; Dest n6], Mul;
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123 "neon_mla_qqq_8_16",
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124 [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
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125 "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long",
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126 [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n6)], Mul_2cycle;
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127 "neon_mla_qqq_32_qqd_32_scalar",
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128 [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (3, n6)], Mul_4cycle;
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129 (* vmul, vqdmulh, vqrdmulh *)
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130 (* vmul, vqdmul *)
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131 "neon_mul_ddd_16_scalar_32_16_long_scalar",
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132 [Source_n n2; Source_m n1; Dest n6], Mul;
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133 "neon_mul_qqd_32_scalar",
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134 [Source_n n2; Source_m n1; Dest_n_after (3, n6)], Mul_4cycle;
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135 (* vmla, vmls *)
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136 (* vmla, vmla, vqdmla, vqdmls *)
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137 "neon_mla_ddd_16_scalar_qdd_32_16_long_scalar",
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138 [Source_n n2; Source_m n1; Source_d n3; Dest n6], Mul;
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139
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140 (* NEON integer shift instructions. *)
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141 (* vshr/vshl immediate, vshr_narrow, vshl_vmvh, vsli_vsri_ddd *)
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142 "neon_shift_1", [Source n1; Dest n3], Shift;
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143 (* vqshl, vrshr immediate; vqshr, vqmov, vrshr, vqrshr narrow;
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144 vqshl_vrshl_vqrshl_ddd *)
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145 "neon_shift_2", [Source n1; Dest n4], Shift;
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146 (* vsli, vsri and vshl for qqq *)
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147 "neon_shift_3", [Source n1; Dest_n_after (1, n3)], Shift_2cycle;
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148 "neon_vshl_ddd", [Source n1; Dest n1], Shift;
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149 "neon_vqshl_vrshl_vqrshl_qqq", [Source n1; Dest_n_after (1, n4)],
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150 Shift_2cycle;
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151 "neon_vsra_vrsra", [Source_m n1; Source_d n3; Dest n6], Shift;
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152
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153 (* NEON floating-point instructions. *)
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154 (* vadd, vsub, vabd, vmul, vceq, vcge, vcgt, vcage, vcagt, vmax, vmin *)
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155 (* vabs, vneg, vceqz, vcgez, vcgtz, vclez, vcltz, vrecpe, vrsqrte, vcvt *)
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156 "neon_fp_vadd_ddd_vabs_dd", [Source n2; Dest n5], Fadd;
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157 "neon_fp_vadd_qqq_vabs_qq", [Source n2; Dest_n_after (1, n5)],
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158 Fadd_2cycle;
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159 (* vsum, fvmx, vfmn *)
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160 "neon_fp_vsum", [Source n1; Dest n5], Fadd;
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161 "neon_fp_vmul_ddd", [Source_n n2; Source_m n1; Dest n5], Fmul;
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162 "neon_fp_vmul_qqd", [Source_n n2; Source_m n1; Dest_n_after (1, n5)],
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163 Fmul_2cycle;
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164 (* vmla, vmls *)
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165 "neon_fp_vmla_ddd",
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166 [Source_n n2; Source_m n2; Source_d n3; Dest n9], Fmul_then_fadd;
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167 "neon_fp_vmla_qqq",
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168 [Source_n n2; Source_m n2; Source_d n3; Dest_n_after (1, n9)],
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169 Fmul_then_fadd_2;
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170 "neon_fp_vmla_ddd_scalar",
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171 [Source_n n2; Source_m n1; Source_d n3; Dest n9], Fmul_then_fadd;
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172 "neon_fp_vmla_qqq_scalar",
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173 [Source_n n2; Source_m n1; Source_d n3; Dest_n_after (1, n9)],
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174 Fmul_then_fadd_2;
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175 "neon_fp_vrecps_vrsqrts_ddd", [Source n2; Dest n9], Fmul_then_fadd;
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176 "neon_fp_vrecps_vrsqrts_qqq", [Source n2; Dest_n_after (1, n9)],
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177 Fmul_then_fadd_2;
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178
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179 (* NEON byte permute instructions. *)
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180 (* vmov; vtrn and vswp for dd; vzip for dd; vuzp for dd; vrev; vext for dd *)
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181 "neon_bp_simple", [Source n1; Dest n2], Permute 1;
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182 (* vswp for qq; vext for qqq; vtbl with {Dn} or {Dn, Dn1};
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183 similarly for vtbx *)
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184 "neon_bp_2cycle", [Source n1; Dest_n_after (1, n2)], Permute 2;
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185 (* all the rest *)
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186 "neon_bp_3cycle", [Source n1; Dest_n_after (2, n2)], Permute 3;
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187
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188 (* NEON load/store instructions. *)
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189 "neon_ldr", [Dest n1], Ls 1;
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190 "neon_str", [Source n1], Ls 1;
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191 "neon_vld1_1_2_regs", [Dest_n_after (1, n1)], Ls 2;
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192 "neon_vld1_3_4_regs", [Dest_n_after (2, n1)], Ls 3;
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193 "neon_vld2_2_regs_vld1_vld2_all_lanes", [Dest_n_after (1, n2)], Ls 2;
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194 "neon_vld2_4_regs", [Dest_n_after (2, n2)], Ls 3;
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195 "neon_vld3_vld4", [Dest_n_after (3, n2)], Ls 4;
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196 "neon_vst1_1_2_regs_vst2_2_regs", [Source n1], Ls 2;
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197 "neon_vst1_3_4_regs", [Source n1], Ls 3;
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198 "neon_vst2_4_regs_vst3_vst4", [Source n1], Ls 4;
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199 "neon_vst3_vst4", [Source n1], Ls 4;
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200 "neon_vld1_vld2_lane", [Source n1; Dest_n_after (2, n2)], Ls 3;
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201 "neon_vld3_vld4_lane", [Source n1; Dest_n_after (4, n2)], Ls 5;
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202 "neon_vst1_vst2_lane", [Source n1], Ls 2;
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203 "neon_vst3_vst4_lane", [Source n1], Ls 3;
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204 "neon_vld3_vld4_all_lanes", [Dest_n_after (1, n2)], Ls 3;
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205
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206 (* NEON register transfer instructions. *)
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207 "neon_mcr", [Dest n2], Permute 1;
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208 "neon_mcr_2_mcrr", [Dest n2], Permute 2;
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209 (* MRC instructions are in the .tpl file. *)
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210 ]
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211
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212 (* Augment the tuples in the availability table with an extra component
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213 that describes the earliest stage where a source operand may be
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214 required. (It is also possible that an entry in the table has no
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215 source requirements.) *)
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216 let calculate_sources =
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217 List.map (fun (name, avail, res) ->
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218 let earliest_stage =
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219 List.fold_left
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220 (fun cur -> fun info ->
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221 match info with
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222 Source stage
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223 | Source_n stage
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224 | Source_m stage
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225 | Source_d stage ->
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226 (match cur with
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227 None -> Some stage
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228 | Some stage' when stage < stage' -> Some stage
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229 | _ -> cur)
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230 | _ -> cur) None avail
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231 in
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232 (name, avail, res, earliest_stage))
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233
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234 (* Find the stage, if any, at the end of which a group produces a result. *)
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235 let find_dest (attr, avail, _, _) =
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236 try
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237 find_with_result
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238 (fun av -> match av with
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239 Dest st -> Some (Some st)
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240 | Dest_n_after (after, st) -> Some (Some (after + st))
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241 | _ -> None) avail
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242 with Not_found -> None
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243
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244 (* Find the worst-case latency between a producer and a consumer. *)
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245 let worst_case_latency producer (_, _, _, earliest_required) =
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246 let dest = find_dest producer in
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247 match earliest_required, dest with
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248 None, _ ->
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249 (* The consumer doesn't have any source requirements. *)
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250 None
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251 | _, None ->
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252 (* The producer doesn't produce any results (e.g. a store insn). *)
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253 None
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254 | Some consumed, Some produced -> Some (produced - consumed + 1)
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255
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256 (* Helper function for below. *)
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257 let latency_calc f producer (_, avail, _, _) =
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258 try
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259 let source_avail = find_with_result f avail in
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260 match find_dest producer with
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261 None ->
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262 (* The producer does not produce a result. *)
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263 Some 0
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264 | Some produced ->
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265 let latency = produced - source_avail + 1 in
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266 (* Latencies below zero are raised to zero since we don't have
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267 delay slots. *)
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268 if latency < 0 then Some 0 else Some latency
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269 with Not_found -> None
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270
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271 (* Find any Rm latency between a producer and a consumer. If no
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272 Rm source requirement is explicitly specified for the consumer,
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273 return "positive infinity". Also return "positive infinity" if
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274 the latency matches the supplied worst-case latency for this
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275 producer. *)
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276 let get_m_latency producer consumer =
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277 match latency_calc (fun av -> match av with Source_m stage -> Some stage
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278 | _ -> None) producer consumer
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279 with None -> [] | Some latency -> [(Guard_only_m, latency)]
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280
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281 (* Likewise for Rn. *)
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282 let get_n_latency producer consumer =
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283 match latency_calc (fun av -> match av with Source_n stage -> Some stage
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284 | _ -> None) producer consumer
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285 with None -> [] | Some latency -> [(Guard_only_n, latency)]
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286
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287 (* Likewise for Rd. *)
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288 let get_d_latency producer consumer =
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289 match
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290 latency_calc (fun av -> match av with Source_d stage -> Some stage
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291 | _ -> None) producer consumer
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292 with None -> [] | Some latency -> [(Guard_only_d, latency)]
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293
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294 (* Given a producer and a consumer, work out the latency of the producer
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295 to the consumer in each of the four cases (availability information
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296 permitting) identified at the top of this file. Return the
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297 consumer, the worst-case unguarded latency and any guarded latencies. *)
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298 let calculate_latencies producer consumer =
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299 let worst = worst_case_latency producer consumer in
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300 let m_latency = get_m_latency producer consumer in
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301 let n_latency = get_n_latency producer consumer in
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302 let d_latency = get_d_latency producer consumer in
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303 (consumer, worst, m_latency @ n_latency @ d_latency)
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304
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305 (* Helper function for below. *)
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306 let pick_latency largest worst guards =
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307 let guards =
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308 match worst with
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309 None -> guards
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310 | Some worst -> (Guard_none, worst) :: guards
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311 in
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312 if List.length guards = 0 then None else
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313 let total_latency =
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314 List.fold_left (fun acc -> fun (_, latency) -> acc + latency) 0 guards
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315 in
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316 let average_latency = (float_of_int total_latency) /.
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317 (float_of_int (List.length guards)) in
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318 let rounded_latency = int_of_float (ceil average_latency) in
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319 if rounded_latency = largest then None
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320 else Some (Guard_none, rounded_latency)
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321
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322 (* Collate all bypasses for a particular producer as required in
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323 worst_case_latencies_and_bypasses. (By this stage there is a maximum
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324 of one bypass from this producer to any particular consumer listed
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325 in LATENCIES.) Use a hash table to collate bypasses with the
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326 same latency and guard. *)
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327 let collate_bypasses (producer_name, _, _, _) largest latencies =
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328 let ht = Hashtbl.create 42 in
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329 let keys = ref [] in
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330 List.iter (
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331 fun ((consumer, _, _, _), worst, guards) ->
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332 (* Find out which latency to use. Ignoring latencies that match
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333 the *overall* worst-case latency for this producer (which will
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334 be in define_insn_reservation), we have to examine:
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335 1. the latency with no guard between this producer and this
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336 consumer; and
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337 2. any guarded latency. *)
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338 let guard_latency_opt = pick_latency largest worst guards in
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339 match guard_latency_opt with
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340 None -> ()
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341 | Some (guard, latency) ->
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342 begin
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343 (if (try ignore (Hashtbl.find ht (guard, latency)); false
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344 with Not_found -> true) then
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345 keys := (guard, latency) :: !keys);
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346 Hashtbl.add ht (guard, latency) consumer
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347 end
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348 ) latencies;
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349 (* The hash table now has bypasses collated so that ones with the
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350 same latency and guard have the same keys. Walk through all the
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351 keys, extract the associated bypasses, and concatenate the names
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352 of the consumers for each bypass. *)
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353 List.map (
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354 fun ((guard, latency) as key) ->
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355 let consumers = Hashtbl.find_all ht key in
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356 (producer_name,
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357 String.concat ",\\\n " consumers,
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358 latency,
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359 guard)
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360 ) !keys
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361
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362 (* For every producer, find the worst-case latency between it and
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363 *any* consumer. Also determine (if such a thing exists) the
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364 lowest-latency bypass from each producer to each consumer. Group
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365 the output in such a way that all bypasses with the same producer
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366 and latency are together, and so that bypasses with the worst-case
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367 latency are ignored. *)
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368 let worst_case_latencies_and_bypasses =
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369 let rec f (worst_acc, bypasses_acc) prev xs =
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370 match xs with
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371 [] -> (worst_acc, bypasses_acc)
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372 | ((producer_name, producer_avail, res_string, _) as producer)::next ->
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373 (* For this particular producer, work out the latencies between
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374 it and every consumer. *)
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375 let latencies =
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376 List.fold_left (fun acc -> fun consumer ->
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377 (calculate_latencies producer consumer) :: acc)
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378 [] (prev @ xs)
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379 in
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380 (* Now work out what the overall worst case latency was for this
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381 particular producer. *)
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382 match latencies with
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383 [] -> assert false
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384 | _ ->
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385 let comp_fn (_, l1, _) (_, l2, _) =
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386 if l1 > l2 then -1 else if l1 = l2 then 0 else 1
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387 in
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388 let largest =
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389 match List.hd (List.sort comp_fn latencies) with
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390 (_, None, _) -> 0 (* Producer has no consumers. *)
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391 | (_, Some worst, _) -> worst
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392 in
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393 (* Having got the largest latency, collect all bypasses for
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394 this producer and filter out those with that larger
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395 latency. Record the others for later emission. *)
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396 let bypasses = collate_bypasses producer largest latencies in
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397 (* Go on to process remaining producers, having noted
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398 the result for this one. *)
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399 f ((producer_name, producer_avail, largest,
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400 res_string) :: worst_acc,
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401 bypasses @ bypasses_acc)
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402 (prev @ [producer]) next
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403 in
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404 f ([], []) []
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405
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406 (* Emit a helpful comment for a define_insn_reservation. *)
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407 let write_comment producer avail =
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408 let seen_source = ref false in
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409 let describe info =
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410 let read = if !seen_source then "" else "read " in
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411 match info with
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412 Source stage ->
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413 seen_source := true;
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414 Printf.printf "%stheir source operands at N%d" read stage
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415 | Source_n stage ->
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416 seen_source := true;
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417 Printf.printf "%stheir (D|Q)n operands at N%d" read stage
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418 | Source_m stage ->
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419 seen_source := true;
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420 Printf.printf "%stheir (D|Q)m operands at N%d" read stage
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421 | Source_d stage ->
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422 Printf.printf "%stheir (D|Q)d operands at N%d" read stage
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423 | Dest stage ->
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424 Printf.printf "produce a result at N%d" stage
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425 | Dest_n_after (after, stage) ->
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426 Printf.printf "produce a result at N%d on cycle %d" stage (after + 1)
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427 in
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428 Printf.printf ";; Instructions using this reservation ";
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429 let rec f infos x =
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430 let sep = if x mod 2 = 1 then "" else "\n;;" in
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431 match infos with
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432 [] -> assert false
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433 | [info] -> describe info; Printf.printf ".\n"
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434 | info::(_::[] as infos) ->
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435 describe info; Printf.printf ", and%s " sep; f infos (x+1)
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436 | info::infos -> describe info; Printf.printf ",%s " sep; f infos (x+1)
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437 in
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438 f avail 0
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439
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440 (* Emit a define_insn_reservation for each producer. The latency
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441 written in will be its worst-case latency. *)
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442 let emit_insn_reservations =
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443 List.iter (
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444 fun (producer, avail, latency, reservation) ->
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445 write_comment producer avail;
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446 Printf.printf "(define_insn_reservation \"%s\" %d\n" producer latency;
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447 Printf.printf " (and (eq_attr \"tune\" \"cortexa8\")\n";
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448 Printf.printf " (eq_attr \"neon_type\" \"%s\"))\n" producer;
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449 let str =
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450 match reservation with
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451 Mul -> "dp" | Mul_2cycle -> "dp_2" | Mul_4cycle -> "dp_4"
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452 | Shift -> "dp" | Shift_2cycle -> "dp_2"
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453 | ALU -> "dp" | ALU_2cycle -> "dp_2"
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454 | Fmul -> "dp" | Fmul_2cycle -> "dp_2"
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455 | Fadd -> "fadd" | Fadd_2cycle -> "fadd_2"
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456 | Ls 1 -> "ls"
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457 | Ls n -> "ls_" ^ (string_of_int n)
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458 | Permute 1 -> "perm"
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459 | Permute n -> "perm_" ^ (string_of_int n)
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460 | Fmul_then_fadd -> "fmul_then_fadd"
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461 | Fmul_then_fadd_2 -> "fmul_then_fadd_2"
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462 in
|
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463 Printf.printf " \"cortex_a8_neon_%s\")\n\n" str
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|
|
464 )
|
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465
|
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|
466 (* Given a guard description, return the name of the C function to
|
|
|
467 be used as the guard for define_bypass. *)
|
|
|
468 let guard_fn g =
|
|
|
469 match g with
|
|
|
470 Guard_only_m -> "arm_neon_only_m_dependency"
|
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471 | Guard_only_n -> "arm_neon_only_n_dependency"
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472 | Guard_only_d -> "arm_neon_only_d_dependency"
|
|
|
473 | Guard_none -> assert false
|
|
|
474
|
|
|
475 (* Emit a define_bypass for each bypass. *)
|
|
|
476 let emit_bypasses =
|
|
|
477 List.iter (
|
|
|
478 fun (producer, consumers, latency, guard) ->
|
|
|
479 Printf.printf "(define_bypass %d \"%s\"\n" latency producer;
|
|
|
480 if guard = Guard_none then
|
|
|
481 Printf.printf " \"%s\")\n\n" consumers
|
|
|
482 else
|
|
|
483 begin
|
|
|
484 Printf.printf " \"%s\"\n" consumers;
|
|
|
485 Printf.printf " \"%s\")\n\n" (guard_fn guard)
|
|
|
486 end
|
|
|
487 )
|
|
|
488
|
|
|
489 (* Program entry point. *)
|
|
|
490 let main =
|
|
|
491 let table = calculate_sources availability_table in
|
|
|
492 let worst_cases, bypasses = worst_case_latencies_and_bypasses table in
|
|
|
493 emit_insn_reservations (List.rev worst_cases);
|
|
|
494 Printf.printf ";; Exceptions to the default latencies.\n\n";
|
|
|
495 emit_bypasses bypasses
|
|
|
496
|
