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1 ;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors.
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2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "ppc7xx,ppc7xxfp")
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21 (define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx")
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22 (define_cpu_unit "fpu_7xx" "ppc7xxfp")
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23 (define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx")
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24 (define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx")
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25 (define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx")
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26
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27 ;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU
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28 ;; IU1 can perform all integer operations
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29 ;; IU2 can perform all integer operations except imul and idiv
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30 ;; LSU 2 stage pipelined
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31 ;; FPU 3 stage pipelined
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32 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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33 ;; In-order execution
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34
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35
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36 ;; The PPC750 user's manual recommends that to reduce branch mispredictions,
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37 ;; the insn that sets CR bits should be separated from the branch insn
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38 ;; that evaluates them. There is no advantage have more than 10 cycles
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39 ;; of separation.
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40 ;; This could be artificially achieved by exaggerating the latency of
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41 ;; compare insns but at the expense of a poorer schedule.
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42
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43 ;; Branches go straight to the BPU. All other insns are handled
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44 ;; by a dispatch unit which can issue a max of 2 insns per cycle.
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45 (define_reservation "ppc750_du" "du1_7xx|du2_7xx")
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46 (define_reservation "ppc7400_vec_du" "vdu_7xx")
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47
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48 (define_insn_reservation "ppc750-load" 2
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49 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\
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50 load_ux,load_u,fpload,fpload_ux,fpload_u,\
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51 vecload,load_l")
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52 (eq_attr "cpu" "ppc750,ppc7400"))
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53 "ppc750_du,lsu_7xx")
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54
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55 (define_insn_reservation "ppc750-store" 2
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56 (and (eq_attr "type" "store,store_ux,store_u,\
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57 fpstore,fpstore_ux,fpstore_u,vecstore")
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58 (eq_attr "cpu" "ppc750,ppc7400"))
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59 "ppc750_du,lsu_7xx")
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60
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61 (define_insn_reservation "ppc750-storec" 8
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62 (and (eq_attr "type" "store_c")
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63 (eq_attr "cpu" "ppc750,ppc7400"))
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64 "ppc750_du,lsu_7xx")
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65
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66 (define_insn_reservation "ppc750-integer" 1
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67 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\
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68 trap,var_shift_rotate,cntlz,exts")
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69 (eq_attr "cpu" "ppc750,ppc7400"))
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70 "ppc750_du,iu1_7xx|iu2_7xx")
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71
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72 (define_insn_reservation "ppc750-two" 1
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73 (and (eq_attr "type" "two")
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74 (eq_attr "cpu" "ppc750,ppc7400"))
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75 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
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76
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77 (define_insn_reservation "ppc750-three" 1
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78 (and (eq_attr "type" "three")
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79 (eq_attr "cpu" "ppc750,ppc7400"))
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80 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
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81
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82 (define_insn_reservation "ppc750-imul" 4
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83 (and (eq_attr "type" "imul,imul_compare")
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84 (eq_attr "cpu" "ppc750,ppc7400"))
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85 "ppc750_du,iu1_7xx*4")
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86
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87 (define_insn_reservation "ppc750-imul2" 3
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88 (and (eq_attr "type" "imul2")
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89 (eq_attr "cpu" "ppc750,ppc7400"))
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90 "ppc750_du,iu1_7xx*2")
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91
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92 (define_insn_reservation "ppc750-imul3" 2
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93 (and (eq_attr "type" "imul3")
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94 (eq_attr "cpu" "ppc750,ppc7400"))
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95 "ppc750_du,iu1_7xx")
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96
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97 (define_insn_reservation "ppc750-idiv" 19
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98 (and (eq_attr "type" "idiv")
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99 (eq_attr "cpu" "ppc750,ppc7400"))
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100 "ppc750_du,iu1_7xx*19")
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101
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102 (define_insn_reservation "ppc750-compare" 2
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103 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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104 var_delayed_compare")
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105 (eq_attr "cpu" "ppc750,ppc7400"))
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106 "ppc750_du,(iu1_7xx|iu2_7xx)")
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107
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108 (define_insn_reservation "ppc750-fpcompare" 2
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109 (and (eq_attr "type" "fpcompare")
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110 (eq_attr "cpu" "ppc750,ppc7400"))
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111 "ppc750_du,fpu_7xx")
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112
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113 (define_insn_reservation "ppc750-fp" 3
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114 (and (eq_attr "type" "fp")
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115 (eq_attr "cpu" "ppc750,ppc7400"))
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116 "ppc750_du,fpu_7xx")
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117
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118 (define_insn_reservation "ppc750-dmul" 4
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119 (and (eq_attr "type" "dmul")
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120 (eq_attr "cpu" "ppc750"))
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121 "ppc750_du,fpu_7xx*2")
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122
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123 (define_insn_reservation "ppc7400-dmul" 3
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124 (and (eq_attr "type" "dmul")
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125 (eq_attr "cpu" "ppc7400"))
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126 "ppc750_du,fpu_7xx")
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127
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128 ; Divides are not pipelined
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129 (define_insn_reservation "ppc750-sdiv" 17
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130 (and (eq_attr "type" "sdiv")
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131 (eq_attr "cpu" "ppc750,ppc7400"))
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132 "ppc750_du,fpu_7xx*17")
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133
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134 (define_insn_reservation "ppc750-ddiv" 31
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135 (and (eq_attr "type" "ddiv")
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136 (eq_attr "cpu" "ppc750,ppc7400"))
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137 "ppc750_du,fpu_7xx*31")
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138
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139 (define_insn_reservation "ppc750-mfcr" 2
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140 (and (eq_attr "type" "mfcr,mtcr")
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141 (eq_attr "cpu" "ppc750,ppc7400"))
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142 "ppc750_du,iu1_7xx")
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143
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144 (define_insn_reservation "ppc750-crlogical" 3
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145 (and (eq_attr "type" "cr_logical,delayed_cr")
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146 (eq_attr "cpu" "ppc750,ppc7400"))
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147 "nothing,sru_7xx*2")
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148
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149 (define_insn_reservation "ppc750-mtjmpr" 2
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150 (and (eq_attr "type" "mtjmpr,isync,sync")
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151 (eq_attr "cpu" "ppc750,ppc7400"))
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152 "nothing,sru_7xx*2")
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153
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154 (define_insn_reservation "ppc750-mfjmpr" 3
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155 (and (eq_attr "type" "mfjmpr")
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156 (eq_attr "cpu" "ppc750,ppc7400"))
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157 "nothing,sru_7xx*2")
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158
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159 (define_insn_reservation "ppc750-jmpreg" 1
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160 (and (eq_attr "type" "jmpreg,branch,isync")
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161 (eq_attr "cpu" "ppc750,ppc7400"))
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162 "nothing,bpu_7xx")
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163
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164 ;; Altivec
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165 (define_insn_reservation "ppc7400-vecsimple" 1
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166 (and (eq_attr "type" "vecsimple,veccmp")
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167 (eq_attr "cpu" "ppc7400"))
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168 "ppc750_du,ppc7400_vec_du,veccmplx_7xx")
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169
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170 (define_insn_reservation "ppc7400-veccomplex" 4
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171 (and (eq_attr "type" "veccomplex")
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172 (eq_attr "cpu" "ppc7400"))
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173 "ppc750_du,ppc7400_vec_du,veccmplx_7xx")
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174
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175 (define_insn_reservation "ppc7400-vecfloat" 4
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176 (and (eq_attr "type" "vecfloat")
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177 (eq_attr "cpu" "ppc7400"))
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178 "ppc750_du,ppc7400_vec_du,veccmplx_7xx")
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179
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180 (define_insn_reservation "ppc7400-vecperm" 2
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181 (and (eq_attr "type" "vecperm")
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182 (eq_attr "cpu" "ppc7400"))
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183 "ppc750_du,ppc7400_vec_du,vecperm_7xx")
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184
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