--- a/gcc/config/arm/arm1020e.md	Sun Aug 21 07:07:55 2011 +0900
+++ b/gcc/config/arm/arm1020e.md	Fri Oct 27 22:46:09 2017 +0900
@@ -1,5 +1,5 @@
 ;; ARM 1020E & ARM 1022E Pipeline Description
-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
+;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
 ;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
 ;;
 ;; This file is part of GCC.
@@ -58,7 +58,7 @@
 
 ;; ALU instructions require three cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
@@ -66,13 +66,21 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "1020alu_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu"))
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_sreg,alus_sreg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple,no_insn"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "1020alu_shift_op" 1 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu_shift"))
+      (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       extend,mov_shift,mvn_shift"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; ALU operations with a shift-by-register operand
@@ -81,7 +89,9 @@
 ;; the execute stage.
 (define_insn_reservation "1020alu_shift_reg_op" 2 
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "alu_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "1020a_e*2,1020a_m,1020a_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -96,7 +106,7 @@
 ;; until after the memory stage.
 (define_insn_reservation "1020mult1" 2
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "insn" "smulxy,smulwy"))
+      (eq_attr "type" "smulxy,smulwy"))
  "1020a_e,1020a_m,1020a_w")
 
 ;; The "smlaxy" and "smlawx" instructions require two iterations through
@@ -104,7 +114,7 @@
 ;; the execute stage.
 (define_insn_reservation "1020mult2" 2
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "insn" "smlaxy,smlalxy,smlawx"))
+      (eq_attr "type" "smlaxy,smlalxy,smlawx"))
  "1020a_e*2,1020a_m,1020a_w")
 
 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
@@ -112,7 +122,7 @@
 ;; the memory stage.
 (define_insn_reservation "1020mult3" 3
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "insn" "smlalxy,mul,mla"))
+      (eq_attr "type" "smlalxy,mul,mla"))
  "1020a_e*2,1020a_m,1020a_w")
 
 ;; The "muls" and "mlas" instructions loop in the execute stage for
@@ -120,7 +130,7 @@
 ;; available after three iterations.
 (define_insn_reservation "1020mult4" 3
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "insn" "muls,mlas"))
+      (eq_attr "type" "muls,mlas"))
  "1020a_e*4,1020a_m,1020a_w")
 
 ;; Long multiply instructions that produce two registers of
@@ -135,7 +145,7 @@
 ;; available after the memory cycle.
 (define_insn_reservation "1020mult5" 4
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "insn" "umull,umlal,smull,smlal"))
+      (eq_attr "type" "umull,umlal,smull,smlal"))
  "1020a_e*3,1020a_m,1020a_w")
 
 ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
@@ -143,7 +153,7 @@
 ;; The value result is available after four iterations.
 (define_insn_reservation "1020mult6" 4
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "insn" "umulls,umlals,smulls,smlals"))
+      (eq_attr "type" "umulls,umlals,smulls,smlals"))
  "1020a_e*5,1020a_m,1020a_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -166,12 +176,12 @@
 
 (define_insn_reservation "1020load1_op" 2
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "load_byte,load1"))
+      (eq_attr "type" "load_byte,load_4"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "1020store1_op" 0
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "store1"))
+      (eq_attr "type" "store_4"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 ;; A load's result can be stored by an immediately following store
@@ -201,22 +211,22 @@
 
 (define_insn_reservation "1020load2_op" 2
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "load2"))
+      (eq_attr "type" "load_8"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "1020store2_op" 0
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "store2"))
+      (eq_attr "type" "store_8"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "1020load34_op" 3
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "load3,load4"))
+      (eq_attr "type" "load_12,load_16"))
  "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
 
 (define_insn_reservation "1020store34_op" 0
  (and (eq_attr "tune" "arm1020e,arm1022e")
-      (eq_attr "type" "store3,store4"))
+      (eq_attr "type" "store_12,store_16"))
  "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -236,13 +246,14 @@
       (eq_attr "type" "branch"))
  "1020a_e")
 
-;; The latency for a call is not predictable.  Therefore, we use 32 as
-;; roughly equivalent to positive infinity.
+;; The latency for a call is not predictable.  Therefore, we model as blocking
+;; execution for a number of cycles but we can't do anything more accurate
+;; than that.
 
 (define_insn_reservation "1020call_op" 32
  (and (eq_attr "tune" "arm1020e,arm1022e")
       (eq_attr "type" "call"))
- "1020a_e*32")
+ "1020a_e*4")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; VFP
@@ -269,7 +280,7 @@
 ;; first execute state.  We model this by using 1020a_e in the first cycle.
 (define_insn_reservation "v10_ffarith" 5
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
+      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
  "1020a_e+v10_fmac")
 
 (define_insn_reservation "v10_farith" 5
@@ -279,23 +290,23 @@
 
 (define_insn_reservation "v10_cvt" 5
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "f_cvt"))
+      (eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i"))
  "1020a_e+v10_fmac")
 
 (define_insn_reservation "v10_fmul" 6
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "fmuls,fmacs,fmuld,fmacd"))
+      (eq_attr "type" "fmuls,fmacs,ffmas,fmuld,fmacd,ffmad"))
  "1020a_e+v10_fmac*2")
 
 (define_insn_reservation "v10_fdivs" 18
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "fdivs"))
- "1020a_e+v10_ds*14")
+      (eq_attr "type" "fdivs, fsqrts"))
+ "1020a_e+v10_ds*4")
 
 (define_insn_reservation "v10_fdivd" 32
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "fdivd"))
- "1020a_e+v10_fmac+v10_ds*28")
+      (eq_attr "type" "fdivd, fsqrtd"))
+ "1020a_e+v10_fmac+v10_ds*4")
 
 (define_insn_reservation "v10_floads" 4
  (and (eq_attr "vfp10" "yes")
@@ -315,7 +326,7 @@
 
 (define_insn_reservation "v10_c2v" 4
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "r_2_f"))
+      (eq_attr "type" "f_mcr,f_mcrr"))
  "1020a_e+1020l_e+v10_ls1,v10_ls2")
 
 (define_insn_reservation "v10_fstores" 1
@@ -330,7 +341,7 @@
 
 (define_insn_reservation "v10_v2c" 1
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "f_2_r"))
+      (eq_attr "type" "f_mrc,f_mrrc"))
  "1020a_e+1020l_e,1020l_m,1020l_w")
 
 (define_insn_reservation "v10_to_cpsr" 2