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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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2 ; RUN: opt < %s -indvars -S | FileCheck %s
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3 ; This is a collection of tests specifically for LFTR of multiple exit loops.
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4 ; The actual LFTR performed is trivial so as to focus on the loop structure
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5 ; aspects.
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6
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7 ; Provide legal integer types.
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8 target datalayout = "n8:16:32:64"
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9
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10 @A = external global i32
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11
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12 define void @analyzeable_early_exit(i32 %n) {
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13 ; CHECK-LABEL: @analyzeable_early_exit(
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14 ; CHECK-NEXT: entry:
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15 ; CHECK-NEXT: br label [[LOOP:%.*]]
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16 ; CHECK: loop:
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17 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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18 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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19 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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20 ; CHECK: latch:
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21 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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22 ; CHECK-NEXT: store i32 [[IV]], i32* @A
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23 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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24 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LOOP]], label [[EXIT]]
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25 ; CHECK: exit:
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26 ; CHECK-NEXT: ret void
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27 ;
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28 entry:
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29 br label %loop
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30
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31 loop:
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32 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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33 %earlycnd = icmp ult i32 %iv, %n
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34 br i1 %earlycnd, label %latch, label %exit
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35
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36 latch:
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37 %iv.next = add i32 %iv, 1
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38 store i32 %iv, i32* @A
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39 %c = icmp ult i32 %iv.next, 1000
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40 br i1 %c, label %loop, label %exit
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41
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42 exit:
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43 ret void
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44 }
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45
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46 define void @unanalyzeable_early_exit() {
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47 ; CHECK-LABEL: @unanalyzeable_early_exit(
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48 ; CHECK-NEXT: entry:
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49 ; CHECK-NEXT: br label [[LOOP:%.*]]
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50 ; CHECK: loop:
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51 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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52 ; CHECK-NEXT: [[VOL:%.*]] = load volatile i32, i32* @A
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53 ; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ne i32 [[VOL]], 0
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54 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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55 ; CHECK: latch:
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56 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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57 ; CHECK-NEXT: store i32 [[IV]], i32* @A
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58 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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59 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT]]
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60 ; CHECK: exit:
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61 ; CHECK-NEXT: ret void
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62 ;
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63 entry:
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64 br label %loop
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65
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66 loop:
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67 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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68 %vol = load volatile i32, i32* @A
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69 %earlycnd = icmp ne i32 %vol, 0
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70 br i1 %earlycnd, label %latch, label %exit
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71
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72 latch:
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73 %iv.next = add i32 %iv, 1
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74 store i32 %iv, i32* @A
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75 %c = icmp ult i32 %iv.next, 1000
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76 br i1 %c, label %loop, label %exit
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77
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78 exit:
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79 ret void
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80 }
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81
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82
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83 define void @multiple_early_exits(i32 %n, i32 %m) {
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84 ; CHECK-LABEL: @multiple_early_exits(
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85 ; CHECK-NEXT: entry:
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86 ; CHECK-NEXT: br label [[LOOP:%.*]]
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87 ; CHECK: loop:
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88 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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89 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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90 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[CONTINUE:%.*]], label [[EXIT:%.*]]
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91 ; CHECK: continue:
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92 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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93 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV]], [[M:%.*]]
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94 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LATCH]], label [[EXIT]]
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95 ; CHECK: latch:
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96 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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97 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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98 ; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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99 ; CHECK-NEXT: br i1 [[EXITCOND2]], label [[LOOP]], label [[EXIT]]
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100 ; CHECK: exit:
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101 ; CHECK-NEXT: ret void
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102 ;
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103 entry:
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104 br label %loop
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105
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106 loop:
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107 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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108 %earlycnd = icmp ult i32 %iv, %n
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109 br i1 %earlycnd, label %continue, label %exit
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110
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111 continue:
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112 store volatile i32 %iv, i32* @A
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113 %earlycnd2 = icmp ult i32 %iv, %m
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114 br i1 %earlycnd2, label %latch, label %exit
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115
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116 latch:
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117 %iv.next = add i32 %iv, 1
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118 store volatile i32 %iv, i32* @A
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119 %c = icmp ult i32 %iv.next, 1000
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120 br i1 %c, label %loop, label %exit
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121
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122 exit:
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123 ret void
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124 }
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125
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126 ; Note: This slightly odd form is what indvars itself produces for multiple
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127 ; exits without a side effect between them.
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128 define void @compound_early_exit(i32 %n, i32 %m) {
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129 ; CHECK-LABEL: @compound_early_exit(
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130 ; CHECK-NEXT: entry:
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173
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131 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[M:%.*]], [[N:%.*]]
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132 ; CHECK-NEXT: [[UMIN:%.*]] = select i1 [[TMP0]], i32 [[M]], i32 [[N]]
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150
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133 ; CHECK-NEXT: br label [[LOOP:%.*]]
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134 ; CHECK: loop:
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135 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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173
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136 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[UMIN]]
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137 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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150
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138 ; CHECK: latch:
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139 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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140 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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173
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141 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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142 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LOOP]], label [[EXIT]]
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150
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143 ; CHECK: exit:
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144 ; CHECK-NEXT: ret void
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145 ;
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146 entry:
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147 br label %loop
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148
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149 loop:
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150 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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151 %earlycnd = icmp ult i32 %iv, %n
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152 %earlycnd2 = icmp ult i32 %iv, %m
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153 %and = and i1 %earlycnd, %earlycnd2
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154 br i1 %and, label %latch, label %exit
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155
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156 latch:
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157 %iv.next = add i32 %iv, 1
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158 store volatile i32 %iv, i32* @A
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159 %c = icmp ult i32 %iv.next, 1000
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160 br i1 %c, label %loop, label %exit
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161
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162 exit:
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163 ret void
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164 }
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165
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166
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167 define void @unanalyzeable_latch(i32 %n) {
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168 ; CHECK-LABEL: @unanalyzeable_latch(
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169 ; CHECK-NEXT: entry:
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170 ; CHECK-NEXT: br label [[LOOP:%.*]]
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171 ; CHECK: loop:
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172 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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173 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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174 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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175 ; CHECK: latch:
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176 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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177 ; CHECK-NEXT: store i32 [[IV]], i32* @A
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178 ; CHECK-NEXT: [[VOL:%.*]] = load volatile i32, i32* @A
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179 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[VOL]], 1000
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180 ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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181 ; CHECK: exit:
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182 ; CHECK-NEXT: ret void
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183 ;
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184 entry:
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185 br label %loop
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186
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187 loop:
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188 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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189 %earlycnd = icmp ult i32 %iv, %n
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190 br i1 %earlycnd, label %latch, label %exit
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191
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192 latch:
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193 %iv.next = add i32 %iv, 1
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194 store i32 %iv, i32* @A
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195 %vol = load volatile i32, i32* @A
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196 %c = icmp ult i32 %vol, 1000
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197 br i1 %c, label %loop, label %exit
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198
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199 exit:
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200 ret void
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201 }
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202
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203 define void @single_exit_no_latch(i32 %n) {
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204 ; CHECK-LABEL: @single_exit_no_latch(
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205 ; CHECK-NEXT: entry:
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206 ; CHECK-NEXT: br label [[LOOP:%.*]]
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207 ; CHECK: loop:
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208 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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209 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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210 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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211 ; CHECK: latch:
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212 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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213 ; CHECK-NEXT: store i32 [[IV]], i32* @A
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214 ; CHECK-NEXT: br label [[LOOP]]
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215 ; CHECK: exit:
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216 ; CHECK-NEXT: ret void
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217 ;
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218 entry:
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219 br label %loop
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220
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221 loop:
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222 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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223 %earlycnd = icmp ult i32 %iv, %n
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224 br i1 %earlycnd, label %latch, label %exit
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225
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226 latch:
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227 %iv.next = add i32 %iv, 1
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228 store i32 %iv, i32* @A
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229 br label %loop
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230
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231 exit:
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232 ret void
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233 }
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234
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235 ; Multiple exits which could be LFTRed, but the latch itself is not an
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236 ; exiting block.
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237 define void @no_latch_exit(i32 %n, i32 %m) {
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238 ; CHECK-LABEL: @no_latch_exit(
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239 ; CHECK-NEXT: entry:
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240 ; CHECK-NEXT: br label [[LOOP:%.*]]
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241 ; CHECK: loop:
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242 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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243 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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244 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[CONTINUE:%.*]], label [[EXIT:%.*]]
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245 ; CHECK: continue:
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246 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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247 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV]], [[M:%.*]]
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248 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LATCH]], label [[EXIT]]
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249 ; CHECK: latch:
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250 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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251 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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252 ; CHECK-NEXT: br label [[LOOP]]
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253 ; CHECK: exit:
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254 ; CHECK-NEXT: ret void
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255 ;
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256 entry:
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257 br label %loop
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258
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259 loop:
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260 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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261 %earlycnd = icmp ult i32 %iv, %n
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262 br i1 %earlycnd, label %continue, label %exit
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263
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264 continue:
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265 store volatile i32 %iv, i32* @A
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266 %earlycnd2 = icmp ult i32 %iv, %m
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267 br i1 %earlycnd2, label %latch, label %exit
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268
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269 latch:
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270 store volatile i32 %iv, i32* @A
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271 %iv.next = add i32 %iv, 1
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272 br label %loop
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273
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274 exit:
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275 ret void
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276 }
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277
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278 ;; Show the value of multiple exit LFTR (being able to eliminate all but
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279 ;; one IV when exit tests involve multiple IVs).
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280 define void @combine_ivs(i32 %n) {
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281 ; CHECK-LABEL: @combine_ivs(
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282 ; CHECK-NEXT: entry:
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283 ; CHECK-NEXT: br label [[LOOP:%.*]]
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284 ; CHECK: loop:
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285 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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286 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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287 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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288 ; CHECK: latch:
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289 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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290 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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291 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV_NEXT]], 999
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292 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LOOP]], label [[EXIT]]
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293 ; CHECK: exit:
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294 ; CHECK-NEXT: ret void
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295 ;
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296 entry:
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297 br label %loop
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298
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299 loop:
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300 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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301 %iv2 = phi i32 [ 1, %entry], [ %iv2.next, %latch]
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302 %earlycnd = icmp ult i32 %iv, %n
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303 br i1 %earlycnd, label %latch, label %exit
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304
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305 latch:
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306 %iv.next = add i32 %iv, 1
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307 %iv2.next = add i32 %iv2, 1
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308 store volatile i32 %iv, i32* @A
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309 %c = icmp ult i32 %iv2.next, 1000
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310 br i1 %c, label %loop, label %exit
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311
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312 exit:
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313 ret void
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314 }
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315
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316 ; We can remove the decrementing IV entirely
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317 define void @combine_ivs2(i32 %n) {
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318 ; CHECK-LABEL: @combine_ivs2(
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319 ; CHECK-NEXT: entry:
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320 ; CHECK-NEXT: br label [[LOOP:%.*]]
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321 ; CHECK: loop:
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322 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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323 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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324 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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325 ; CHECK: latch:
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326 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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327 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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328 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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329 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LOOP]], label [[EXIT]]
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330 ; CHECK: exit:
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331 ; CHECK-NEXT: ret void
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332 ;
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333 entry:
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334 br label %loop
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335
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336 loop:
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337 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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338 %iv2 = phi i32 [ 1000, %entry], [ %iv2.next, %latch]
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339 %earlycnd = icmp ult i32 %iv, %n
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340 br i1 %earlycnd, label %latch, label %exit
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341
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342 latch:
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343 %iv.next = add i32 %iv, 1
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344 %iv2.next = sub i32 %iv2, 1
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345 store volatile i32 %iv, i32* @A
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346 %c = icmp ugt i32 %iv2.next, 0
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347 br i1 %c, label %loop, label %exit
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348
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349 exit:
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350 ret void
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351 }
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352
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353 ; An example where we can eliminate an f(i) computation entirely
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354 ; from a multiple exit loop with LFTR.
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355 define void @simplify_exit_test(i32 %n) {
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356 ; CHECK-LABEL: @simplify_exit_test(
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357 ; CHECK-NEXT: entry:
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358 ; CHECK-NEXT: br label [[LOOP:%.*]]
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359 ; CHECK: loop:
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360 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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361 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV]], [[N:%.*]]
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362 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LATCH]], label [[EXIT:%.*]]
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363 ; CHECK: latch:
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364 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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365 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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366 ; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[IV_NEXT]], 65
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367 ; CHECK-NEXT: br i1 [[EXITCOND1]], label [[LOOP]], label [[EXIT]]
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368 ; CHECK: exit:
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369 ; CHECK-NEXT: ret void
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370 ;
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371 entry:
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372 br label %loop
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373
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374 loop:
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375 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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376 %earlycnd = icmp ult i32 %iv, %n
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377 br i1 %earlycnd, label %latch, label %exit
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378
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379 latch:
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380 %iv.next = add i32 %iv, 1
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381 %fx = shl i32 %iv, 4
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382 store volatile i32 %iv, i32* @A
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383 %c = icmp ult i32 %fx, 1024
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384 br i1 %c, label %loop, label %exit
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385
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386 exit:
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387 ret void
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388 }
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389
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390
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391 ; Another example where we can remove an f(i) type computation, but this
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392 ; time in a loop w/o a statically computable exit count.
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393 define void @simplify_exit_test2(i32 %n) {
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394 ; CHECK-LABEL: @simplify_exit_test2(
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395 ; CHECK-NEXT: entry:
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396 ; CHECK-NEXT: br label [[LOOP:%.*]]
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397 ; CHECK: loop:
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398 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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399 ; CHECK-NEXT: [[VOL:%.*]] = load volatile i32, i32* @A
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400 ; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ne i32 [[VOL]], 0
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401 ; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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402 ; CHECK: latch:
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403 ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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404 ; CHECK-NEXT: [[FX:%.*]] = udiv i32 [[IV]], 4
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405 ; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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406 ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[FX]], 1024
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407 ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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408 ; CHECK: exit:
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409 ; CHECK-NEXT: ret void
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410 ;
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411 entry:
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412 br label %loop
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413
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414 loop:
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415 %iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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416 %vol = load volatile i32, i32* @A
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417 %earlycnd = icmp ne i32 %vol, 0
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418 br i1 %earlycnd, label %latch, label %exit
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419
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420 latch:
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421 %iv.next = add i32 %iv, 1
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422 %fx = udiv i32 %iv, 4
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423 store volatile i32 %iv, i32* @A
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424 %c = icmp ult i32 %fx, 1024
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425 br i1 %c, label %loop, label %exit
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426
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427 exit:
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428 ret void
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429 }
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430
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431 ; Demonstrate a case where two nested loops share a single exiting block.
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432 ; The key point is that the exit count is *different* for the two loops, and
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433 ; thus we can't rewrite the exit for the outer one. There are three sub-cases
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434 ; which can happen here: a) the outer loop has a backedge taken count of zero
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435 ; (for the case where we know the inner exit is known taken), b) the exit is
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436 ; known never taken (but may have an exit count outside the range of the IV)
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437 ; or c) the outer loop has an unanalyzable exit count (where we can't tell).
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438 define void @nested(i32 %n) {
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439 ; CHECK-LABEL: @nested(
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440 ; CHECK-NEXT: entry:
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441 ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N:%.*]], 1
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442 ; CHECK-NEXT: br label [[OUTER:%.*]]
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443 ; CHECK: outer:
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444 ; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV1_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
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445 ; CHECK-NEXT: store volatile i32 [[IV1]], i32* @A
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446 ; CHECK-NEXT: [[IV1_NEXT]] = add nuw nsw i32 [[IV1]], 1
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447 ; CHECK-NEXT: br label [[INNER:%.*]]
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448 ; CHECK: inner:
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449 ; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[OUTER]] ], [ [[IV2_NEXT:%.*]], [[INNER_LATCH:%.*]] ]
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450 ; CHECK-NEXT: store volatile i32 [[IV2]], i32* @A
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451 ; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i32 [[IV2]], 1
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452 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2]], 20
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453 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNER_LATCH]], label [[EXIT_LOOPEXIT:%.*]]
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454 ; CHECK: inner_latch:
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455 ; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp ne i32 [[IV2_NEXT]], [[TMP0]]
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456 ; CHECK-NEXT: br i1 [[EXITCOND2]], label [[INNER]], label [[OUTER_LATCH]]
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457 ; CHECK: outer_latch:
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458 ; CHECK-NEXT: [[EXITCOND3:%.*]] = icmp ne i32 [[IV1_NEXT]], 21
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459 ; CHECK-NEXT: br i1 [[EXITCOND3]], label [[OUTER]], label [[EXIT_LOOPEXIT1:%.*]]
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460 ; CHECK: exit.loopexit:
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461 ; CHECK-NEXT: br label [[EXIT:%.*]]
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462 ; CHECK: exit.loopexit1:
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463 ; CHECK-NEXT: br label [[EXIT]]
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464 ; CHECK: exit:
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465 ; CHECK-NEXT: ret void
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466 ;
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467 entry:
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468 br label %outer
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469
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470 outer:
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471 %iv1 = phi i32 [ 0, %entry ], [ %iv1.next, %outer_latch ]
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472 store volatile i32 %iv1, i32* @A
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473 %iv1.next = add i32 %iv1, 1
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474 br label %inner
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475
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476 inner:
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477 %iv2 = phi i32 [ 0, %outer ], [ %iv2.next, %inner_latch ]
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478 store volatile i32 %iv2, i32* @A
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479 %iv2.next = add i32 %iv2, 1
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480 %innertest = icmp ult i32 %iv2, 20
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481 br i1 %innertest, label %inner_latch, label %exit
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482
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483 inner_latch:
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484 %innertestb = icmp ult i32 %iv2, %n
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485 br i1 %innertestb, label %inner, label %outer_latch
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486
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487 outer_latch:
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488 %outertest = icmp ult i32 %iv1, 20
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489 br i1 %outertest, label %outer, label %exit
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490
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491 exit:
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492 ret void
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493 }
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