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annotate docs/AMDGPUUsage.rst @ 120:1172e4bd9c6f

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1 ==============================
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2 User Guide for AMDGPU Back-end
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3 ==============================
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4
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5 Introduction
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6 ============
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7
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8 The AMDGPU back-end provides ISA code generation for AMD GPUs, starting with
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9 the R600 family up until the current Volcanic Islands (GCN Gen 3).
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10
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11 Refer to `AMDGPU section in Architecture & Platform Information for Compiler Writers <CompilerWriterInfo.html#amdgpu>`_
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12 for additional documentation.
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13
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14 Conventions
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15 ===========
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16
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17 Address Spaces
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18 --------------
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19
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20 The AMDGPU back-end uses the following address space mapping:
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21
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22 ============= ============================================
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23 Address Space Memory Space
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24 ============= ============================================
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25 0 Private
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26 1 Global
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27 2 Constant
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28 3 Local
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29 4 Generic (Flat)
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30 5 Region
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31 ============= ============================================
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32
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33 The terminology in the table, aside from the region memory space, is from the
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34 OpenCL standard.
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35
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36
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37 Assembler
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38 =========
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39
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40 AMDGPU backend has LLVM-MC based assembler which is currently in development.
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41 It supports Southern Islands ISA, Sea Islands and Volcanic Islands.
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42
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43 This document describes general syntax for instructions and operands. For more
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44 information about instructions, their semantics and supported combinations
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45 of operands, refer to one of Instruction Set Architecture manuals.
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46
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47 An instruction has the following syntax (register operands are
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48 normally comma-separated while extra operands are space-separated):
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49
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50 *<opcode> <register_operand0>, ... <extra_operand0> ...*
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51
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52
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53 Operands
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54 --------
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55
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56 The following syntax for register operands is supported:
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57
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58 * SGPR registers: s0, ... or s[0], ...
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59 * VGPR registers: v0, ... or v[0], ...
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60 * TTMP registers: ttmp0, ... or ttmp[0], ...
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61 * Special registers: exec (exec_lo, exec_hi), vcc (vcc_lo, vcc_hi), flat_scratch (flat_scratch_lo, flat_scratch_hi)
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62 * Special trap registers: tba (tba_lo, tba_hi), tma (tma_lo, tma_hi)
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63 * Register pairs, quads, etc: s[2:3], v[10:11], ttmp[5:6], s[4:7], v[12:15], ttmp[4:7], s[8:15], ...
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64 * Register lists: [s0, s1], [ttmp0, ttmp1, ttmp2, ttmp3]
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65 * Register index expressions: v[2*2], s[1-1:2-1]
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66 * 'off' indicates that an operand is not enabled
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67
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68 The following extra operands are supported:
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69
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70 * offset, offset0, offset1
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71 * idxen, offen bits
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72 * glc, slc, tfe bits
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73 * waitcnt: integer or combination of counter values
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74 * VOP3 modifiers:
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75
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76 - abs (\| \|), neg (\-)
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77
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78 * DPP modifiers:
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79
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80 - row_shl, row_shr, row_ror, row_rol
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81 - row_mirror, row_half_mirror, row_bcast
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82 - wave_shl, wave_shr, wave_ror, wave_rol, quad_perm
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83 - row_mask, bank_mask, bound_ctrl
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84
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85 * SDWA modifiers:
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86
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87 - dst_sel, src0_sel, src1_sel (BYTE_N, WORD_M, DWORD)
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88 - dst_unused (UNUSED_PAD, UNUSED_SEXT, UNUSED_PRESERVE)
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89 - abs, neg, sext
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90
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91 DS Instructions Examples
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92 ------------------------
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93
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94 .. code-block:: nasm
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95
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96 ds_add_u32 v2, v4 offset:16
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97 ds_write_src2_b64 v2 offset0:4 offset1:8
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98 ds_cmpst_f32 v2, v4, v6
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99 ds_min_rtn_f64 v[8:9], v2, v[4:5]
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100
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101
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102 For full list of supported instructions, refer to "LDS/GDS instructions" in ISA Manual.
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103
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104 FLAT Instruction Examples
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105 --------------------------
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106
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107 .. code-block:: nasm
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108
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109 flat_load_dword v1, v[3:4]
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110 flat_store_dwordx3 v[3:4], v[5:7]
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111 flat_atomic_swap v1, v[3:4], v5 glc
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112 flat_atomic_cmpswap v1, v[3:4], v[5:6] glc slc
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113 flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc
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114
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115 For full list of supported instructions, refer to "FLAT instructions" in ISA Manual.
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116
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117 MUBUF Instruction Examples
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118 ---------------------------
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119
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120 .. code-block:: nasm
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121
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122 buffer_load_dword v1, off, s[4:7], s1
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123 buffer_store_dwordx4 v[1:4], v2, ttmp[4:7], s1 offen offset:4 glc tfe
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124 buffer_store_format_xy v[1:2], off, s[4:7], s1
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125 buffer_wbinvl1
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126 buffer_atomic_inc v1, v2, s[8:11], s4 idxen offset:4 slc
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127
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128 For full list of supported instructions, refer to "MUBUF Instructions" in ISA Manual.
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129
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130 SMRD/SMEM Instruction Examples
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131 -------------------------------
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132
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133 .. code-block:: nasm
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134
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135 s_load_dword s1, s[2:3], 0xfc
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136 s_load_dwordx8 s[8:15], s[2:3], s4
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137 s_load_dwordx16 s[88:103], s[2:3], s4
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138 s_dcache_inv_vol
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139 s_memtime s[4:5]
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140
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141 For full list of supported instructions, refer to "Scalar Memory Operations" in ISA Manual.
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142
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143 SOP1 Instruction Examples
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144 --------------------------
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145
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146 .. code-block:: nasm
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147
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148 s_mov_b32 s1, s2
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149 s_mov_b64 s[0:1], 0x80000000
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150 s_cmov_b32 s1, 200
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151 s_wqm_b64 s[2:3], s[4:5]
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152 s_bcnt0_i32_b64 s1, s[2:3]
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153 s_swappc_b64 s[2:3], s[4:5]
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154 s_cbranch_join s[4:5]
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155
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156 For full list of supported instructions, refer to "SOP1 Instructions" in ISA Manual.
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158 SOP2 Instruction Examples
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159 -------------------------
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160
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161 .. code-block:: nasm
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162
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163 s_add_u32 s1, s2, s3
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164 s_and_b64 s[2:3], s[4:5], s[6:7]
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165 s_cselect_b32 s1, s2, s3
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166 s_andn2_b32 s2, s4, s6
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167 s_lshr_b64 s[2:3], s[4:5], s6
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168 s_ashr_i32 s2, s4, s6
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169 s_bfm_b64 s[2:3], s4, s6
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170 s_bfe_i64 s[2:3], s[4:5], s6
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171 s_cbranch_g_fork s[4:5], s[6:7]
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172
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173 For full list of supported instructions, refer to "SOP2 Instructions" in ISA Manual.
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174
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175 SOPC Instruction Examples
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176 --------------------------
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177
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178 .. code-block:: nasm
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179
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180 s_cmp_eq_i32 s1, s2
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181 s_bitcmp1_b32 s1, s2
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182 s_bitcmp0_b64 s[2:3], s4
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183 s_setvskip s3, s5
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184
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185 For full list of supported instructions, refer to "SOPC Instructions" in ISA Manual.
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186
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187 SOPP Instruction Examples
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188 --------------------------
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189
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190 .. code-block:: nasm
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191
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192 s_barrier
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193 s_nop 2
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194 s_endpgm
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195 s_waitcnt 0 ; Wait for all counters to be 0
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196 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0) ; Equivalent to above
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197 s_waitcnt vmcnt(1) ; Wait for vmcnt counter to be 1.
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198 s_sethalt 9
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199 s_sleep 10
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200 s_sendmsg 0x1
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201 s_sendmsg sendmsg(MSG_INTERRUPT)
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202 s_trap 1
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203
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204 For full list of supported instructions, refer to "SOPP Instructions" in ISA Manual.
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205
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206 Unless otherwise mentioned, little verification is performed on the operands
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207 of SOPP Instrucitons, so it is up to the programmer to be familiar with the
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208 range or acceptable values.
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209
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210 Vector ALU Instruction Examples
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211 -------------------------------
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212
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213 For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
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214 the assembler will automatically use optimal encoding based on its operands.
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215 To force specific encoding, one can add a suffix to the opcode of the instruction:
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216
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217 * _e32 for 32-bit VOP1/VOP2/VOPC
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218 * _e64 for 64-bit VOP3
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219 * _dpp for VOP_DPP
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220 * _sdwa for VOP_SDWA
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221
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222 VOP1/VOP2/VOP3/VOPC examples:
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223
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224 .. code-block:: nasm
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225
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226 v_mov_b32 v1, v2
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227 v_mov_b32_e32 v1, v2
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228 v_nop
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229 v_cvt_f64_i32_e32 v[1:2], v2
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230 v_floor_f32_e32 v1, v2
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231 v_bfrev_b32_e32 v1, v2
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232 v_add_f32_e32 v1, v2, v3
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233 v_mul_i32_i24_e64 v1, v2, 3
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234 v_mul_i32_i24_e32 v1, -3, v3
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235 v_mul_i32_i24_e32 v1, -100, v3
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236 v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
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237 v_max_f16_e32 v1, v2, v3
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238
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239 VOP_DPP examples:
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240
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241 .. code-block:: nasm
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242
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243 v_mov_b32 v0, v0 quad_perm:[0,2,1,1]
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244 v_sin_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
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245 v_mov_b32 v0, v0 wave_shl:1
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246 v_mov_b32 v0, v0 row_mirror
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247 v_mov_b32 v0, v0 row_bcast:31
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248 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0
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249 v_add_f32 v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
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250 v_max_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
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251
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252 VOP_SDWA examples:
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253
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254 .. code-block:: nasm
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255
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256 v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
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257 v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
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258 v_sin_f32 v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1
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259 v_fract_f32 v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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260 v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
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261
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262 For full list of supported instructions, refer to "Vector ALU instructions".
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263
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264 HSA Code Object Directives
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265 --------------------------
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266
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267 AMDGPU ABI defines auxiliary data in output code object. In assembly source,
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268 one can specify them with assembler directives.
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269
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270 .hsa_code_object_version major, minor
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271 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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272
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273 *major* and *minor* are integers that specify the version of the HSA code
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274 object that will be generated by the assembler.
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275
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276 .hsa_code_object_isa [major, minor, stepping, vendor, arch]
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277 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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278
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279 *major*, *minor*, and *stepping* are all integers that describe the instruction
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280 set architecture (ISA) version of the assembly program.
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281
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282 *vendor* and *arch* are quoted strings. *vendor* should always be equal to
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283 "AMD" and *arch* should always be equal to "AMDGPU".
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284
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285 By default, the assembler will derive the ISA version, *vendor*, and *arch*
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286 from the value of the -mcpu option that is passed to the assembler.
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287
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288 .amdgpu_hsa_kernel (name)
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289 ^^^^^^^^^^^^^^^^^^^^^^^^^
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290
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291 This directives specifies that the symbol with given name is a kernel entry point
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292 (label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.
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293
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294 .amd_kernel_code_t
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295 ^^^^^^^^^^^^^^^^^^
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296
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297 This directive marks the beginning of a list of key / value pairs that are used
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298 to specify the amd_kernel_code_t object that will be emitted by the assembler.
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299 The list must be terminated by the *.end_amd_kernel_code_t* directive. For
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300 any amd_kernel_code_t values that are unspecified a default value will be
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301 used. The default value for all keys is 0, with the following exceptions:
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302
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303 - *kernel_code_version_major* defaults to 1.
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304 - *machine_kind* defaults to 1.
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305 - *machine_version_major*, *machine_version_minor*, and
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306 *machine_version_stepping* are derived from the value of the -mcpu option
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307 that is passed to the assembler.
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308 - *kernel_code_entry_byte_offset* defaults to 256.
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309 - *wavefront_size* defaults to 6.
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310 - *kernarg_segment_alignment*, *group_segment_alignment*, and
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311 *private_segment_alignment* default to 4. Note that alignments are specified
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312 as a power of two, so a value of **n** means an alignment of 2^ **n**.
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313
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314 The *.amd_kernel_code_t* directive must be placed immediately after the
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315 function label and before any instructions.
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316
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317 For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
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318 comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.
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319
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320 Here is an example of a minimal amd_kernel_code_t specification:
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321
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322 .. code-block:: none
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323
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324 .hsa_code_object_version 1,0
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325 .hsa_code_object_isa
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326
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327 .hsatext
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328 .globl hello_world
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329 .p2align 8
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330 .amdgpu_hsa_kernel hello_world
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331
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332 hello_world:
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333
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334 .amd_kernel_code_t
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335 enable_sgpr_kernarg_segment_ptr = 1
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336 is_ptr64 = 1
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337 compute_pgm_rsrc1_vgprs = 0
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338 compute_pgm_rsrc1_sgprs = 0
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339 compute_pgm_rsrc2_user_sgpr = 2
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340 kernarg_segment_byte_size = 8
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341 wavefront_sgpr_count = 2
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342 workitem_vgpr_count = 3
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343 .end_amd_kernel_code_t
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344
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345 s_load_dwordx2 s[0:1], s[0:1] 0x0
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346 v_mov_b32 v0, 3.14159
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347 s_waitcnt lgkmcnt(0)
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348 v_mov_b32 v1, s0
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349 v_mov_b32 v2, s1
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350 flat_store_dword v[1:2], v0
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351 s_endpgm
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352 .Lfunc_end0:
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353 .size hello_world, .Lfunc_end0-hello_world