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1 //===-- LanaiDelaySlotFiller.cpp - Lanai delay slot filler ----------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Simple pass to fills delay slots with useful instructions.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "Lanai.h"
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15 #include "LanaiTargetMachine.h"
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16 #include "llvm/ADT/SmallSet.h"
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17 #include "llvm/ADT/Statistic.h"
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18 #include "llvm/CodeGen/MachineFunctionPass.h"
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19 #include "llvm/CodeGen/MachineInstrBuilder.h"
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20 #include "llvm/Support/CommandLine.h"
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21 #include "llvm/Target/TargetInstrInfo.h"
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22
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23 using namespace llvm;
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24
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25 #define DEBUG_TYPE "delay-slot-filler"
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26
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27 STATISTIC(FilledSlots, "Number of delay slots filled");
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28
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29 static cl::opt<bool>
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30 NopDelaySlotFiller("lanai-nop-delay-filler", cl::init(false),
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31 cl::desc("Fill Lanai delay slots with NOPs."),
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32 cl::Hidden);
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33
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34 namespace {
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35 struct Filler : public MachineFunctionPass {
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36 // Target machine description which we query for reg. names, data
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37 // layout, etc.
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38 const TargetInstrInfo *TII;
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39 const TargetRegisterInfo *TRI;
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40 MachineBasicBlock::instr_iterator LastFiller;
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41
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42 static char ID;
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43 explicit Filler() : MachineFunctionPass(ID) {}
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44
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45 StringRef getPassName() const override { return "Lanai Delay Slot Filler"; }
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46
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47 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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48
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49 bool runOnMachineFunction(MachineFunction &MF) override {
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50 const LanaiSubtarget &Subtarget = MF.getSubtarget<LanaiSubtarget>();
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51 TII = Subtarget.getInstrInfo();
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52 TRI = Subtarget.getRegisterInfo();
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53
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54 bool Changed = false;
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55 for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
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56 ++FI)
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57 Changed |= runOnMachineBasicBlock(*FI);
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58 return Changed;
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59 }
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60
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61 MachineFunctionProperties getRequiredProperties() const override {
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62 return MachineFunctionProperties().set(
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63 MachineFunctionProperties::Property::NoVRegs);
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64 }
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65
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66 void insertDefsUses(MachineBasicBlock::instr_iterator MI,
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67 SmallSet<unsigned, 32> &RegDefs,
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68 SmallSet<unsigned, 32> &RegUses);
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69
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70 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
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71
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72 bool delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
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73 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
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74 SmallSet<unsigned, 32> &RegUses);
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75
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76 bool findDelayInstr(MachineBasicBlock &MBB,
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77 MachineBasicBlock::instr_iterator Slot,
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78 MachineBasicBlock::instr_iterator &Filler);
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79 };
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80 char Filler::ID = 0;
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81 } // end of anonymous namespace
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82
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83 // createLanaiDelaySlotFillerPass - Returns a pass that fills in delay
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84 // slots in Lanai MachineFunctions
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85 FunctionPass *
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86 llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine & /*tm*/) {
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87 return new Filler();
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88 }
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89
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90 // runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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91 // There is one or two delay slot per delayed instruction.
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92 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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93 bool Changed = false;
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94 LastFiller = MBB.instr_end();
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95
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96 for (MachineBasicBlock::instr_iterator I = MBB.instr_begin();
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97 I != MBB.instr_end(); ++I) {
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98 if (I->getDesc().hasDelaySlot()) {
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99 MachineBasicBlock::instr_iterator InstrWithSlot = I;
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100 MachineBasicBlock::instr_iterator J = I;
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101
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102 // Treat RET specially as it is only instruction with 2 delay slots
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103 // generated while all others generated have 1 delay slot.
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104 if (I->getOpcode() == Lanai::RET) {
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105 // RET is generated as part of epilogue generation and hence we know
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106 // what the two instructions preceding it are and that it is safe to
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107 // insert RET above them.
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108 MachineBasicBlock::reverse_instr_iterator RI = ++I.getReverse();
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109 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
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110 RI->getOperand(0).getReg() == Lanai::FP &&
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111 RI->getOperand(1).isReg() &&
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112 RI->getOperand(1).getReg() == Lanai::FP &&
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113 RI->getOperand(2).isImm() && RI->getOperand(2).getImm() == -8);
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114 ++RI;
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115 assert(RI->getOpcode() == Lanai::ADD_I_LO &&
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116 RI->getOperand(0).isReg() &&
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117 RI->getOperand(0).getReg() == Lanai::SP &&
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118 RI->getOperand(1).isReg() &&
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119 RI->getOperand(1).getReg() == Lanai::FP);
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120 MachineBasicBlock::instr_iterator FI = RI.getReverse();
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121 MBB.splice(std::next(I), &MBB, FI, I);
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122 FilledSlots += 2;
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123 } else {
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124 if (!NopDelaySlotFiller && findDelayInstr(MBB, I, J)) {
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125 MBB.splice(std::next(I), &MBB, J);
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126 } else {
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127 BuildMI(MBB, std::next(I), DebugLoc(), TII->get(Lanai::NOP));
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128 }
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129 ++FilledSlots;
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130 }
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131
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132 Changed = true;
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133 // Record the filler instruction that filled the delay slot.
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134 // The instruction after it will be visited in the next iteration.
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135 LastFiller = ++I;
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136
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137 // Bundle the delay slot filler to InstrWithSlot so that the machine
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138 // verifier doesn't expect this instruction to be a terminator.
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139 MIBundleBuilder(MBB, InstrWithSlot, std::next(LastFiller));
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140 }
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141 }
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142 return Changed;
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143 }
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144
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145 bool Filler::findDelayInstr(MachineBasicBlock &MBB,
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146 MachineBasicBlock::instr_iterator Slot,
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147 MachineBasicBlock::instr_iterator &Filler) {
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148 SmallSet<unsigned, 32> RegDefs;
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149 SmallSet<unsigned, 32> RegUses;
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150
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151 insertDefsUses(Slot, RegDefs, RegUses);
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152
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153 bool SawLoad = false;
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154 bool SawStore = false;
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155
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156 for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();
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157 I != MBB.instr_rend(); ++I) {
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158 // skip debug value
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159 if (I->isDebugValue())
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160 continue;
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161
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162 // Convert to forward iterator.
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163 MachineBasicBlock::instr_iterator FI = I.getReverse();
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164
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165 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isLabel() ||
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166 FI == LastFiller || I->isPseudo())
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167 break;
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168
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169 if (delayHasHazard(FI, SawLoad, SawStore, RegDefs, RegUses)) {
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170 insertDefsUses(FI, RegDefs, RegUses);
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171 continue;
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172 }
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173 Filler = FI;
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174 return true;
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175 }
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176 return false;
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177 }
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178
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179 bool Filler::delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
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180 bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
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181 SmallSet<unsigned, 32> &RegUses) {
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182 if (MI->isImplicitDef() || MI->isKill())
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183 return true;
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184
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185 // Loads or stores cannot be moved past a store to the delay slot
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186 // and stores cannot be moved past a load.
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187 if (MI->mayLoad()) {
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188 if (SawStore)
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189 return true;
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190 SawLoad = true;
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191 }
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192
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193 if (MI->mayStore()) {
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194 if (SawStore)
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195 return true;
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196 SawStore = true;
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197 if (SawLoad)
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198 return true;
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199 }
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200
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201 assert((!MI->isCall() && !MI->isReturn()) &&
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202 "Cannot put calls or returns in delay slot.");
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203
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204 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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205 const MachineOperand &MO = MI->getOperand(I);
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206 unsigned Reg;
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207
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208 if (!MO.isReg() || !(Reg = MO.getReg()))
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209 continue; // skip
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210
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211 if (MO.isDef()) {
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212 // check whether Reg is defined or used before delay slot.
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213 if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
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214 return true;
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215 }
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216 if (MO.isUse()) {
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217 // check whether Reg is defined before delay slot.
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218 if (isRegInSet(RegDefs, Reg))
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219 return true;
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220 }
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221 }
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222 return false;
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223 }
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224
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225 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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226 void Filler::insertDefsUses(MachineBasicBlock::instr_iterator MI,
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227 SmallSet<unsigned, 32> &RegDefs,
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228 SmallSet<unsigned, 32> &RegUses) {
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229 // If MI is a call or return, just examine the explicit non-variadic operands.
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230 MCInstrDesc MCID = MI->getDesc();
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231 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
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232 : MI->getNumOperands();
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233 for (unsigned I = 0; I != E; ++I) {
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234 const MachineOperand &MO = MI->getOperand(I);
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235 unsigned Reg;
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236
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237 if (!MO.isReg() || !(Reg = MO.getReg()))
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238 continue;
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239
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240 if (MO.isDef())
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241 RegDefs.insert(Reg);
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242 else if (MO.isUse())
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243 RegUses.insert(Reg);
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244 }
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245
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246 // Call & return instructions defines SP implicitly. Implicit defines are not
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247 // included in the RegDefs set of calls but instructions modifying SP cannot
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248 // be inserted in the delay slot of a call/return as these instructions are
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249 // expanded to multiple instructions with SP modified before the branch that
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250 // has the delay slot.
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251 if (MI->isCall() || MI->isReturn())
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252 RegDefs.insert(Lanai::SP);
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253 }
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254
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255 // Returns true if the Reg or its alias is in the RegSet.
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256 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
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257 // Check Reg and all aliased Registers.
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258 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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259 if (RegSet.count(*AI))
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260 return true;
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261 return false;
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262 }
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