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1 //===-- LanaiInstrInfo.td - Target Description for Lanai Target -----------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the Lanai instructions in TableGen format.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 //===----------------------------------------------------------------------===//
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15 // Instruction format superclass
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16 //===----------------------------------------------------------------------===//
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17
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18 include "LanaiInstrFormats.td"
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19
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20 // -------------------------------------------------- //
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21 // Instruction Operands and Patterns
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22 // -------------------------------------------------- //
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23
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24 // These are target-independent nodes, but have target-specific formats.
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25 def SDT_LanaiCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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26 def SDT_LanaiCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
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27 SDTCisVT<1, i32>]>;
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28 def SDT_LanaiCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
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29 def SDT_LanaiSetFlag : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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30 def SDT_LanaiSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
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31 SDTCisSameAs<1, 2>]>;
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32 def SDT_LanaiSetCC : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
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33 SDTCisVT<1, i32>]>;
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34 def SDT_LanaiBrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>,
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35 SDTCisVT<1, i32>]>;
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36 def SDT_LanaiAdjDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
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37 SDTCisVT<1, i32>]>;
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38
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39 def Call : SDNode<"LanaiISD::CALL", SDT_LanaiCall,
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40 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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41 SDNPVariadic]>;
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42 def RetFlag : SDNode<"LanaiISD::RET_FLAG", SDTNone,
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43 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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44 def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_LanaiCallSeqStart,
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45 [SDNPHasChain, SDNPOutGlue]>;
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46 def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_LanaiCallSeqEnd,
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47 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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48 def LanaiSetFlag : SDNode<"LanaiISD::SET_FLAG", SDT_LanaiSetFlag,
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49 [SDNPOutGlue]>;
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50 def LanaiSubbF : SDNode<"LanaiISD::SUBBF", SDT_LanaiSetFlag,
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51 [SDNPOutGlue, SDNPInGlue]>;
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52 def LanaiBrCC : SDNode<"LanaiISD::BR_CC", SDT_LanaiBrCC,
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53 [SDNPHasChain, SDNPInGlue]>;
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54 def LanaiSelectCC : SDNode<"LanaiISD::SELECT_CC", SDT_LanaiSelectCC,
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55 [SDNPInGlue]>;
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56 def LanaiSetCC : SDNode<"LanaiISD::SETCC", SDT_LanaiSetCC,
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57 [SDNPInGlue]>;
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58 def LanaiHi : SDNode<"LanaiISD::HI", SDTIntUnaryOp>;
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59 def LanaiLo : SDNode<"LanaiISD::LO", SDTIntUnaryOp>;
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60 def LanaiSmall : SDNode<"LanaiISD::SMALL", SDTIntUnaryOp>;
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61 def LanaiAdjDynAlloc : SDNode<"LanaiISD::ADJDYNALLOC", SDT_LanaiAdjDynAlloc>;
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62
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63 // Extract bits 0-15 (low-end) of an immediate value.
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64 def LO16 : SDNodeXForm<imm, [{
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65 return CurDAG->getTargetConstant((uint64_t)N->getZExtValue() & 0xffff,
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66 SDLoc(N), MVT::i32);
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67 }]>;
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68
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69 // Extract bits 16-31 (high-end) of an immediate value.
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70 // Transformation function: shift the immediate value down into the low bits.
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71 def HI16 : SDNodeXForm<imm, [{
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72 return CurDAG->getTargetConstant((uint64_t)N->getZExtValue() >> 16, SDLoc(N),
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73 MVT::i32);
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74 }]>;
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75
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76 def NEG : SDNodeXForm<imm, [{
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77 return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
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78 }]>;
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79
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80 def LO21 : SDNodeXForm<imm, [{
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81 return CurDAG->getTargetConstant((uint64_t)N->getZExtValue() & 0x1fffff,
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82 SDLoc(N), MVT::i32);
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83 }]>;
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84
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85 // Branch targets
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86 def BrTargetAsmOperand : AsmOperandClass {
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87 let Name = "BrTarget";
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88 }
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89 def BrTarget : Operand<OtherVT> {
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90 let ParserMatchClass = BrTargetAsmOperand;
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91 let EncoderMethod = "getBranchTargetOpValue";
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92 let DecoderMethod = "decodeBranch";
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93 }
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94
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95 def CallTargetAsmOperand : AsmOperandClass {
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96 let Name = "CallTarget";
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97 }
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98 def CallTarget : Operand<i32> {
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99 let ParserMatchClass = CallTargetAsmOperand;
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100 let EncoderMethod = "getBranchTargetOpValue";
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101 let DecoderMethod = "decodeBranch";
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102 }
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103
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104 def ImmShiftAsmOperand : AsmOperandClass { let Name = "ImmShift"; }
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105 def immShift : Operand<i32>, PatLeaf<(imm), [{
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106 int Imm = N->getSExtValue();
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107 return Imm >= -31 && Imm <= 31;}]> {
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108 let ParserMatchClass = ImmShiftAsmOperand;
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109 let DecoderMethod = "decodeShiftImm";
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110 }
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111
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112 def Imm10AsmOperand : AsmOperandClass { let Name = "Imm10"; }
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113 def imm10 : Operand<i32>, PatLeaf<(imm), [{
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114 return isInt<10>(N->getSExtValue()); }]> {
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115 let ParserMatchClass = Imm10AsmOperand;
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116 }
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117
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118 def LoImm16AsmOperand : AsmOperandClass { let Name = "LoImm16"; }
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119 def i32lo16z : Operand<i32>, PatLeaf<(i32 imm), [{
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120 // i32lo16 predicate - true if the 32-bit immediate has only rightmost 16
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121 // bits set.
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122 return ((N->getZExtValue() & 0xFFFFUL) == N->getZExtValue());}], LO16> {
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123 let ParserMatchClass = LoImm16AsmOperand;
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124 }
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125 def i32neg16 : Operand<i32>, PatLeaf<(i32 imm), [{
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126 // i32neg16 predicate - true if the 32-bit immediate is negative and can
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127 // be represented by a 16 bit integer.
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128 int Imm = N->getSExtValue();
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129 return (Imm < 0) && (isInt<16>(Imm));}], LO16> {
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130 let ParserMatchClass = LoImm16AsmOperand;
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131 }
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132 def i32lo16s : Operand<i32>, PatLeaf<(i32 imm), [{
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133 // i32lo16 predicate - true if the 32-bit immediate has only rightmost 16
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134 // bits set.
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135 return ((int64_t)(N->getSExtValue() & 0xFFFFUL) == N->getSExtValue());}], LO16> {
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136 let ParserMatchClass = LoImm16AsmOperand;
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137 }
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138
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139 def LoImm16AndAsmOperand : AsmOperandClass { let Name = "LoImm16And"; }
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140 def i32lo16and : Operand<i32>, PatLeaf<(i32 imm), [{
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141 // i32lo16 predicate - true if the 32-bit immediate has the rightmost 16
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142 // bits set and the leftmost 16 bits 1's.
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143 return (N->getZExtValue() >= 0xFFFF0000UL);}], LO16> {
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144 let ParserMatchClass = LoImm16AndAsmOperand;
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145 let PrintMethod = "printLo16AndImmOperand";
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146 }
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147
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148 def HiImm16AsmOperand : AsmOperandClass { let Name = "HiImm16"; }
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149 def i32hi16 : Operand<i32>, PatLeaf<(i32 imm), [{
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150 // i32hi16 predicate - true if the 32-bit immediate has only leftmost 16
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151 // bits set.
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152 return ((N->getZExtValue() & 0xFFFF0000UL) == N->getZExtValue());}], HI16> {
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153 let ParserMatchClass = HiImm16AsmOperand;
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154 let PrintMethod = "printHi16ImmOperand";
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155 }
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156
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157 def HiImm16AndAsmOperand : AsmOperandClass { let Name = "HiImm16And"; }
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158 def i32hi16and : Operand<i32>, PatLeaf<(i32 imm), [{
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159 // i32lo16 predicate - true if the 32-bit immediate has the leftmost 16
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160 // bits set and the rightmost 16 bits 1's.
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161 return ((N->getZExtValue() & 0xFFFFUL) == 0xFFFFUL);}], HI16> {
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162 let ParserMatchClass = HiImm16AndAsmOperand;
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163 let PrintMethod = "printHi16AndImmOperand";
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164 }
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165
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166 def LoImm21AsmOperand : AsmOperandClass { let Name = "LoImm21"; }
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167 def i32lo21 : Operand<i32>, PatLeaf<(i32 imm), [{
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168 // i32lo21 predicate - true if the 32-bit immediate has only rightmost 21
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169 // bits set.
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170 return ((N->getZExtValue() & 0x1FFFFFUL) == N->getZExtValue());}], LO21> {
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171 let ParserMatchClass = LoImm21AsmOperand;
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172 }
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173
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174 def AluOp : Operand<i32> {
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175 let PrintMethod = "printAluOperand";
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176 }
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177
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178 // Addressing modes.
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179 def ADDRrr : ComplexPattern<i32, 3, "selectAddrRr", [], []>;
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180 def ADDRri : ComplexPattern<i32, 3, "selectAddrRi", [frameindex], []>;
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181 def ADDRsls : ComplexPattern<i32, 1, "selectAddrSls", [frameindex], []>;
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182 def ADDRspls : ComplexPattern<i32, 3, "selectAddrSpls", [frameindex], []>;
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183
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184 // Address operands
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185 def MemRegImmAsmOperand : AsmOperandClass {
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186 let Name = "MemRegImm";
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187 let ParserMethod = "parseMemoryOperand";
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188 }
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189 def MEMri : Operand<i32> {
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190 let DecoderMethod = "decodeRiMemoryValue";
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191 let EncoderMethod = "getRiMemoryOpValue";
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192 let MIOperandInfo = (ops GPR:$base, i32lo16s:$offset, AluOp:$Opcode);
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193 let ParserMatchClass = MemRegImmAsmOperand;
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194 let PrintMethod = "printMemRiOperand";
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195 }
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196
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197 def MemRegRegAsmOperand : AsmOperandClass {
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198 let Name = "MemRegReg";
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199 let ParserMethod = "parseMemoryOperand";
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200 }
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201 def MEMrr : Operand<i32> {
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202 let DecoderMethod = "decodeRrMemoryValue";
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203 let EncoderMethod = "getRrMemoryOpValue";
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204 let MIOperandInfo = (ops GPR:$Op1, GPR:$Op2, AluOp:$Opcode);
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205 let ParserMatchClass = MemRegRegAsmOperand;
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206 let PrintMethod = "printMemRrOperand";
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207 }
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208
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209 def MemImmAsmOperand : AsmOperandClass {
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210 let Name = "MemImm";
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211 let ParserMethod = "parseMemoryOperand";
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212 }
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213 def MEMi : Operand<i32> {
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214 let MIOperandInfo = (ops i32lo21:$offset);
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215 let ParserMatchClass = MemImmAsmOperand;
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216 let PrintMethod = "printMemImmOperand";
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217 }
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218
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219 def MemSplsAsmOperand : AsmOperandClass {
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220 let Name = "MemSpls";
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221 let ParserMethod = "parseMemoryOperand";
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222 }
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223 def MEMspls : Operand<i32> {
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224 let DecoderMethod = "decodeSplsValue";
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225 let EncoderMethod = "getSplsOpValue";
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226 let MIOperandInfo = (ops GPR:$base, imm10:$offset, AluOp:$Opcode);
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227 let ParserMatchClass = MemSplsAsmOperand;
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228 let PrintMethod = "printMemSplsOperand";
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229 }
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230
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231 def CCOp : Operand<i32> {
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232 let PrintMethod = "printCCOperand";
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233 }
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234
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235 // Predicate operand. Default to 0 = true.
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236 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
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237
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238 def pred : PredicateOperand<i32, (ops i32imm), (ops (i32 0))> {
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239 let PrintMethod = "printPredicateOperand";
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240 let ParserMatchClass = CondCodeOperand;
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241 let DecoderMethod = "decodePredicateOperand";
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242 }
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243
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244 let hasSideEffects = 0, Inst = 0x00000001 in
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245 def NOP : InstLanai<(outs), (ins), "nop", []>;
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246
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247 // Special NOPs to change logging level in vlanai.
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248 let hasSideEffects = 0, Inst = 0x00000002 in
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249 def LOG0 : InstLanai<(outs), (ins), "log_0", []>;
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250 let hasSideEffects = 0, Inst = 0x00000003 in
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251 def LOG1 : InstLanai<(outs), (ins), "log_1", []>;
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252 let hasSideEffects = 0, Inst = 0x00000004 in
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253 def LOG2 : InstLanai<(outs), (ins), "log_2", []>;
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254 let hasSideEffects = 0, Inst = 0x00000005 in
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255 def LOG3 : InstLanai<(outs), (ins), "log_3", []>;
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256 let hasSideEffects = 0, Inst = 0x00000006 in
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257 def LOG4 : InstLanai<(outs), (ins), "log_4", []>;
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258
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259 // Map an SPLS instruction onto itself. All other instructions will be mapped
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260 // onto -1. Used to identify SPLS instructions.
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261 def splsIdempotent : InstrMapping {
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262 let FilterClass = "InstSPLS";
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263 let RowFields = ["AsmString"];
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264 let ColFields = ["PostEncoderMethod"];
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265 let KeyCol = ["adjustPqBitsSpls"];
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266 let ValueCols = [["adjustPqBitsSpls"]];
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267 }
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268
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269 // -------------------------------------------------- //
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270 // ALU instructions
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271 // -------------------------------------------------- //
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272 multiclass ALUbase<bits<3> subOp, string AsmStr, SDNode OpNode,
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273 PatLeaf LoExt, PatLeaf HiExt,
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274 list<dag> loPattern, list<dag> hiPattern> {
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275 // Register Immediate
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276 let H = 0 in
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277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
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278 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
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279 loPattern>;
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280 let H = 1 in
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281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
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282 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
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283 hiPattern>;
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284
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285 }
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286
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287 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
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288 PatLeaf LoExt, PatLeaf HiExt> {
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289 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt, [], []>;
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290
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291 // Register Register
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292 let JJJJJ = 0 in
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293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
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294 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
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295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
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296 }
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297
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298 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
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299 PatLeaf LoExt, PatLeaf HiExt> {
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300 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt,
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301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
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302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
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303
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304 // Register Register
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305 let JJJJJ = 0 in
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306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
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307 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
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308 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
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309 }
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310
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311 // Non flag setting ALU operations
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312 let isAsCheapAsAMove = 1, F = 0 in {
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313 let isCommutable = 1 in {
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314 defm ADD_ : ALUarith<0b000, "add", add, i32lo16z, i32hi16>;
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315 }
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316 defm SUB_ : ALUarith<0b010, "sub", sub, i32lo16z, i32hi16>;
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317 let isCommutable = 1 in {
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318 defm AND_ : ALUlogic<0b100, "and", and, i32lo16and, i32hi16and>;
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319 defm OR_ : ALUlogic<0b101, "or", or, i32lo16z, i32hi16>;
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320 defm XOR_ : ALUlogic<0b110, "xor", xor, i32lo16z, i32hi16>;
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321 }
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322 }
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323
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324 def : Pat<(add GPR:$Rs1, i32lo16z:$imm),
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325 (ADD_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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326
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327 def : Pat<(sub GPR:$Rs1, i32lo16z:$imm),
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328 (SUB_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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329
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330 def : Pat<(add GPR:$Rs1, i32hi16:$imm),
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331 (ADD_I_HI GPR:$Rs1, i32hi16:$imm)>;
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332
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333 def : Pat<(sub GPR:$Rs1, i32hi16:$imm),
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334 (SUB_I_HI GPR:$Rs1, i32hi16:$imm)>;
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335
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336 def : Pat<(i32 i32lo16and:$imm), (AND_I_LO (i32 R1), i32lo16and:$imm)>;
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337 def : Pat<(i32 i32hi16and:$imm), (AND_I_HI (i32 R1), i32hi16and:$imm)>;
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338
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339 // Change add/sub with negative number to sub/add
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340 def : Pat<(add GPR:$Rs1, i32neg16:$imm),
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341 (SUB_I_LO GPR:$Rs1, (NEG $imm))>;
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342 def : Pat<(sub GPR:$Rs1, i32neg16:$imm),
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343 (ADD_I_LO GPR:$Rs1, (NEG $imm))>;
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344
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345 // Flag (incl. carry) setting addition and subtraction
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346 let F = 1, Defs = [SR] in {
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347 defm ADD_F_ : ALUarith<0b000, "add.f", addc, i32lo16z, i32hi16>;
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348 defm SUB_F_ : ALUarith<0b010, "sub.f", subc, i32lo16z, i32hi16>;
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349 }
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350
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351 def : Pat<(addc GPR:$Rs1, i32lo16z:$imm),
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352 (ADD_F_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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353
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354 def : Pat<(subc GPR:$Rs1, i32lo16z:$imm),
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355 (SUB_F_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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356
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357 def : Pat<(addc GPR:$Rs1, i32hi16:$imm),
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358 (ADD_F_I_HI GPR:$Rs1, i32hi16:$imm)>;
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359
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360 def : Pat<(subc GPR:$Rs1, i32hi16:$imm),
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361 (SUB_F_I_HI GPR:$Rs1, i32hi16:$imm)>;
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362
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363 // Carry using addition and subtraction
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364 let F = 0, Uses = [SR] in {
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365 defm ADDC_ : ALUarith<0b001, "addc", adde, i32lo16z, i32hi16>;
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366 defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16z, i32hi16>;
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367 }
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368
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369 def : Pat<(adde GPR:$Rs1, i32lo16z:$imm),
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370 (ADDC_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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371
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372 def : Pat<(sube GPR:$Rs1, i32lo16z:$imm),
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373 (SUBB_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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374
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375 def : Pat<(adde GPR:$Rs1, i32hi16:$imm),
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376 (ADDC_I_HI GPR:$Rs1, i32hi16:$imm)>;
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377
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378 def : Pat<(sube GPR:$Rs1, i32hi16:$imm),
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379 (SUBB_I_HI GPR:$Rs1, i32hi16:$imm)>;
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380
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381 // Flag setting ALU operations
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382 let isAsCheapAsAMove = 1, F = 1, Defs = [SR] in {
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383 let isCommutable = 1 in {
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384 defm AND_F_ : ALUlogic<0b100, "and.f", and, i32lo16and, i32hi16and>;
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385 defm OR_F_ : ALUlogic<0b101, "or.f", or, i32lo16z, i32hi16>;
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386 defm XOR_F_ : ALUlogic<0b110, "xor.f", xor, i32lo16z, i32hi16>;
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387 }
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388 }
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389
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390 let isAsCheapAsAMove = 1, F = 1, Defs = [SR], Uses = [SR] in {
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391 defm ADDC_F_ : ALUarith<0b001, "addc.f", adde, i32lo16z, i32hi16>;
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392 defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16z, i32hi16>;
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393 }
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394
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395 def : Pat<(LanaiSubbF GPR:$Rs1, GPR:$Rs2),
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396 (SUBB_F_R GPR:$Rs1, GPR:$Rs2)>;
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397
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398 def : Pat<(LanaiSubbF GPR:$Rs1, i32lo16z:$imm),
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399 (SUBB_F_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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400
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401 def : Pat<(LanaiSubbF GPR:$Rs1, i32hi16:$imm),
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402 (SUBB_F_I_HI GPR:$Rs1, i32hi16:$imm)>;
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403
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404 def : InstAlias<"mov $src, $dst", (ADD_R GPR:$dst, GPR:$src, R0, 0)>;
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405
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406 let isAsCheapAsAMove = 1, Rs1 = R0.Num, isCodeGenOnly = 1, H = 1, F = 0,
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407 isReMaterializable = 1 in
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408 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16),
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409 "mov\t$imm16, $Rd",
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410 [(set GPR:$Rd, i32hi16:$imm16)]>;
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411
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412 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
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413 def : InstAlias<"mov $imm16, $dst", (ADD_I_HI GPR:$dst, R0, i32hi16:$imm16)>;
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414 def : InstAlias<"mov $imm16, $dst",
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415 (AND_I_LO GPR:$dst, R1, i32lo16and:$imm16)>;
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416 def : InstAlias<"mov $imm16, $dst",
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417 (AND_I_HI GPR:$dst, R1, i32hi16and:$imm16)>;
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418
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419 // Shift instructions
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420 class ShiftRI<string AsmStr, list<dag> Pattern>
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421 : InstRI<0b111, (outs GPR:$Rd), (ins GPR:$Rs1, immShift:$imm16),
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422 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"), Pattern> {
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423 let isReMaterializable = 1;
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424 }
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425
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426 let F = 0 in {
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427 let H = 0 in
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428 def SL_I : ShiftRI<"sh", [(set GPR:$Rd, (shl GPR:$Rs1, immShift:$imm16))]>;
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429 let H = 1 in
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430 def SA_I : ShiftRI<"sha", []>;
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431 }
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432 def : Pat<(srl GPR:$Rs1, immShift:$imm), (SL_I GPR:$Rs1, (NEG $imm))>;
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433 def : Pat<(sra GPR:$Rs1, immShift:$imm), (SA_I GPR:$Rs1, (NEG $imm))>;
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434
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435 let F = 1, Defs = [SR] in {
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436 let H = 0 in
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437 def SL_F_I : ShiftRI<"sh.f", []>;
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438 let H = 1 in
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439 def SA_F_I : ShiftRI<"sha.f", []>;
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440 }
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441
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442 class ShiftRR<string AsmStr, list<dag> Pattern>
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443 : InstRR<0b111, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI), AsmStr,
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444 Pattern>;
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445
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446 let F = 0 in {
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447 let JJJJJ = 0b10000 in
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448 def SHL_R : ShiftRR<"sh$DDDI\t$Rs1, $Rs2, $Rd",
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449 [(set GPR:$Rd, (shl GPR:$Rs1, GPR:$Rs2))]>;
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450 let isCodeGenOnly = 1 in {
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451 let JJJJJ = 0b10000 in
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452 def SRL_R : ShiftRR<"sh$DDDI\t$Rs1, $Rs2, $Rd", []>;
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453 }
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454 let JJJJJ = 0b11000 in
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455 def SRA_R : ShiftRR<"sha$DDDI\t$Rs1, $Rs2, $Rd", []>;
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456 }
|
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457
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458 let F = 1, Defs = [SR] in {
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459 let JJJJJ = 0b10000 in
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460 def SHL_F_R : ShiftRR<"sh.f$DDDI\t$Rs1, $Rs2, $Rd", []>;
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461 let isCodeGenOnly = 1 in {
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462 let JJJJJ = 0b10000 in
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463 def SRL_F_R : ShiftRR<"sh.f$DDDI\t$Rs1, $Rs2, $Rd", []>;
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464 }
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465 let JJJJJ = 0b11000 in
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466 def SRA_F_R : ShiftRR<"sha.f$DDDI\t$Rs1, $Rs2, $Rd", []>;
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467 }
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468
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469 // Expand shift-right operations
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470 def : Pat<(srl GPR:$Rs1, GPR:$Rs2),
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471 (SRL_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
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472 def : Pat<(sra GPR:$Rs1, GPR:$Rs2),
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473 (SRA_R GPR:$Rs1, (SUB_R R0, GPR:$Rs2))>;
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474
|
|
|
475 // -------------------------------------------------- //
|
|
|
476 // LOAD instructions
|
|
|
477 // -------------------------------------------------- //
|
|
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478
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|
479 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
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480 : InstRRM<0b0, (outs GPR:$Rd), (ins MEMrr:$src),
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481 !strconcat(OpcString, "\t$src, $Rd"),
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|
482 [(set (Ty GPR:$Rd), (OpNode ADDRrr:$src))]>,
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|
|
483 Sched<[WriteLD]> {
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|
|
484 bits<20> src;
|
|
|
485
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|
486 let Rs1 = src{19-15};
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|
487 let Rs2 = src{14-10};
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|
488 let P = src{9};
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|
489 let Q = src{8};
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|
490 let BBB = src{7-5};
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|
|
491 let JJJJJ = src{4-0};
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|
|
492 let mayLoad = 1;
|
|
|
493 }
|
|
|
494
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|
|
495 class LoadRI<string OpcString, PatFrag OpNode, ValueType Ty>
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|
|
496 : InstRM<0b0, (outs GPR:$Rd), (ins MEMri:$src),
|
|
|
497 !strconcat(OpcString, "\t$src, $Rd"),
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|
|
498 [(set (Ty GPR:$Rd), (OpNode ADDRri:$src))]>,
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|
|
499 Sched<[WriteLD]> {
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|
|
500 bits<23> src;
|
|
|
501
|
|
|
502 let Itinerary = IIC_LD;
|
|
|
503 let Rs1 = src{22-18};
|
|
|
504 let P = src{17};
|
|
|
505 let Q = src{16};
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|
|
506 let imm16 = src{15-0};
|
|
|
507 let isReMaterializable = 1;
|
|
|
508 let mayLoad = 1;
|
|
|
509 }
|
|
|
510
|
|
|
511 let E = 0 in {
|
|
|
512 let YL = 0b01 in {
|
|
|
513 // uld is used here and ld in the alias as the alias is printed out first if
|
|
|
514 // an alias exist
|
|
|
515 def LDW_RI : LoadRI<"uld", load, i32>;
|
|
|
516 def LDW_RR : LoadRR<"ld", load, i32>;
|
|
|
517 }
|
|
|
518 }
|
|
|
519
|
|
|
520 def : InstAlias<"ld $src, $dst", (LDW_RI GPR:$dst, MEMri:$src)>;
|
|
|
521
|
|
|
522 let E = 1 in {
|
|
|
523 let YL = 0b01 in {
|
|
|
524 def LDWz_RR : LoadRR<"uld", zextloadi32, i32>;
|
|
|
525 }
|
|
|
526 }
|
|
|
527
|
|
|
528 let E = 1 in {
|
|
|
529 let YL = 0b00 in
|
|
|
530 def LDHz_RR : LoadRR<"uld.h", zextloadi16, i32>;
|
|
|
531 let YL = 0b10 in
|
|
|
532 def LDBz_RR : LoadRR<"uld.b", zextloadi8, i32>;
|
|
|
533 }
|
|
|
534
|
|
|
535 let E = 0 in {
|
|
|
536 let YL = 0b00 in
|
|
|
537 def LDHs_RR : LoadRR<"ld.h", sextloadi16, i32>;
|
|
|
538 let YL = 0b10 in
|
|
|
539 def LDBs_RR : LoadRR<"ld.b", sextloadi8, i32>;
|
|
|
540 }
|
|
|
541
|
|
|
542 def LDADDR : InstSLS<0x0, (outs GPR:$Rd), (ins MEMi:$src),
|
|
|
543 "ld\t$src, $Rd",
|
|
|
544 [(set (i32 GPR:$Rd), (load ADDRsls:$src))]>,
|
|
|
545 Sched<[WriteLD]> {
|
|
|
546 bits<21> src;
|
|
|
547
|
|
|
548 let Itinerary = IIC_LD;
|
|
|
549 let msb = src{20-16};
|
|
|
550 let lsb = src{15-0};
|
|
|
551 let isReMaterializable = 1;
|
|
|
552 let mayLoad = 1;
|
|
|
553 }
|
|
|
554
|
|
|
555 class LoadSPLS<string asmstring, PatFrag opNode>
|
|
|
556 : InstSPLS<(outs GPR:$Rd), (ins MEMspls:$src),
|
|
|
557 !strconcat(asmstring, "\t$src, $Rd"),
|
|
|
558 [(set (i32 GPR:$Rd), (opNode ADDRspls:$src))]>,
|
|
|
559 Sched<[WriteLDSW]> {
|
|
|
560 bits<17> src;
|
|
|
561 let Itinerary = IIC_LDSW;
|
|
|
562 let Rs1 = src{16-12};
|
|
|
563 let P = src{11};
|
|
|
564 let Q = src{10};
|
|
|
565 let imm10 = src{9-0};
|
|
|
566 let mayLoad = 1;
|
|
|
567 let isReMaterializable = 1;
|
|
|
568 }
|
|
|
569
|
|
|
570 let Y = 0, S = 0, E = 1 in
|
|
|
571 def LDHz_RI : LoadSPLS<"uld.h", zextloadi16>;
|
|
|
572
|
|
|
573 let Y = 0, S = 0, E = 0 in
|
|
|
574 def LDHs_RI : LoadSPLS<"ld.h", sextloadi16>;
|
|
|
575
|
|
|
576 let Y = 1, S = 0, E = 1 in
|
|
|
577 def LDBz_RI : LoadSPLS<"uld.b", zextloadi8>;
|
|
|
578
|
|
|
579 let Y = 1, S = 0, E = 0 in
|
|
|
580 def LDBs_RI : LoadSPLS<"ld.b", sextloadi8>;
|
|
|
581
|
|
|
582 def SLI : InstSLI<(outs GPR:$Rd), (ins i32lo21:$imm),
|
|
|
583 "mov\t$imm, $Rd",
|
|
|
584 [(set GPR:$Rd, i32lo21:$imm)]> {
|
|
|
585 bits<21> imm;
|
|
|
586
|
|
|
587 let msb = imm{20-16};
|
|
|
588 let lsb = imm{15-0};
|
|
|
589 let isReMaterializable = 1;
|
|
|
590 let isAsCheapAsAMove = 1;
|
|
|
591 }
|
|
|
592
|
|
|
593 // -------------------------------------------------- //
|
|
|
594 // STORE instructions
|
|
|
595 // -------------------------------------------------- //
|
|
|
596
|
|
|
597 class StoreRR<string OpcString, PatFrag OpNode, ValueType Ty>
|
|
|
598 : InstRRM<0b1, (outs), (ins GPR:$Rd, MEMrr:$dst),
|
|
|
599 !strconcat(OpcString, "\t$Rd, $dst"),
|
|
|
600 [(OpNode (Ty GPR:$Rd), ADDRrr:$dst)]>,
|
|
|
601 Sched<[WriteST]> {
|
|
|
602 bits<20> dst;
|
|
|
603
|
|
|
604 let Itinerary = IIC_ST;
|
|
|
605 let Rs1 = dst{19-15};
|
|
|
606 let Rs2 = dst{14-10};
|
|
|
607 let P = dst{9};
|
|
|
608 let Q = dst{8};
|
|
|
609 let BBB = dst{7-5};
|
|
|
610 let JJJJJ = dst{4-0};
|
|
|
611 let mayStore = 1;
|
|
|
612 }
|
|
|
613
|
|
|
614 class StoreRI<string OpcString, PatFrag OpNode, ValueType Ty>
|
|
|
615 : InstRM<0b1, (outs), (ins GPR:$Rd, MEMri:$dst),
|
|
|
616 !strconcat(OpcString, "\t$Rd, $dst"),
|
|
|
617 [(OpNode (Ty GPR:$Rd), ADDRri:$dst)]>,
|
|
|
618 Sched<[WriteST]> {
|
|
|
619 bits<23> dst;
|
|
|
620
|
|
|
621 let Itinerary = IIC_ST;
|
|
|
622 let Rs1 = dst{22-18};
|
|
|
623 let P = dst{17};
|
|
|
624 let Q = dst{16};
|
|
|
625 let imm16 = dst{15-0};
|
|
|
626 let mayStore = 1;
|
|
|
627 }
|
|
|
628
|
|
|
629 let YL = 0b01, E = 0 in {
|
|
|
630 def SW_RR : StoreRR<"st", store, i32>;
|
|
|
631 def SW_RI : StoreRI<"st", store, i32>;
|
|
|
632 }
|
|
|
633
|
|
|
634 let E = 0 in {
|
|
|
635 let YL = 0b00 in
|
|
|
636 def STH_RR : StoreRR<"st.h", truncstorei16, i32>;
|
|
|
637 let YL = 0b10 in
|
|
|
638 def STB_RR : StoreRR<"st.b", truncstorei8, i32>;
|
|
|
639 }
|
|
|
640
|
|
|
641 def STADDR : InstSLS<0x1, (outs), (ins GPR:$Rd, MEMi:$dst),
|
|
|
642 "st\t$Rd, $dst",
|
|
|
643 [(store (i32 GPR:$Rd), ADDRsls:$dst)]>,
|
|
|
644 Sched<[WriteST]> {
|
|
|
645 bits<21> dst;
|
|
|
646
|
|
|
647 let Itinerary = IIC_ST;
|
|
|
648 let msb = dst{20-16};
|
|
|
649 let lsb = dst{15-0};
|
|
|
650 let mayStore = 1;
|
|
|
651 }
|
|
|
652
|
|
|
653 class StoreSPLS<string asmstring, PatFrag opNode>
|
|
|
654 : InstSPLS<(outs), (ins GPR:$Rd, MEMspls:$dst),
|
|
|
655 !strconcat(asmstring, "\t$Rd, $dst"),
|
|
|
656 [(opNode (i32 GPR:$Rd), ADDRspls:$dst)]>,
|
|
|
657 Sched<[WriteSTSW]> {
|
|
|
658 bits<17> dst;
|
|
|
659
|
|
|
660 let Itinerary = IIC_STSW;
|
|
|
661 let Rs1 = dst{16-12};
|
|
|
662 let P = dst{11};
|
|
|
663 let Q = dst{10};
|
|
|
664 let imm10 = dst{9-0};
|
|
|
665 let mayStore = 1;
|
|
|
666 }
|
|
|
667
|
|
|
668 let Y = 0, S = 1, E = 0 in
|
|
|
669 def STH_RI : StoreSPLS<"st.h", truncstorei16>;
|
|
|
670
|
|
|
671 let Y = 1, S = 1, E = 0 in
|
|
|
672 def STB_RI : StoreSPLS<"st.b", truncstorei8>;
|
|
|
673
|
|
|
674 // -------------------------------------------------- //
|
|
|
675 // BRANCH instructions
|
|
|
676 // -------------------------------------------------- //
|
|
|
677
|
|
|
678 let isBranch = 1, isBarrier = 1, isTerminator = 1, hasDelaySlot = 1 in {
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|
|
679 def BT : InstBR<(outs), (ins BrTarget:$addr),
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|
|
680 "bt\t$addr",
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|
681 [(br bb:$addr)]> {
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682 let DDDI = 0b0000;
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|
|
683 }
|
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|
684 let Uses = [SR] in
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|
|
685 def BRCC : InstBR<(outs), (ins BrTarget:$addr, CCOp:$DDDI),
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|
|
686 "b$DDDI\t$addr",
|
|
|
687 [(LanaiBrCC bb:$addr, imm:$DDDI)]>;
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|
|
688
|
|
|
689 let isIndirectBranch = 1 in {
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|
|
690 def JR : InstRR<0b101, (outs), (ins GPR:$Rs2), "bt\t$Rs2",
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|
|
691 [(brind GPR:$Rs2)]> {
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|
692 let Rs1 = R0.Num;
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|
|
693 let Rd = R2.Num;
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|
|
694 let F = 0;
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|
|
695 let JJJJJ = 0;
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|
|
696 let DDDI = 0;
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|
|
697 }
|
|
|
698 }
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|
|
699 }
|
|
|
700
|
|
|
701 // -------------------------------------------------- //
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|
|
702 // Condition/SF instructions
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|
|
703 // -------------------------------------------------- //
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|
|
704
|
|
|
705 // Instructions to set flags used in lowering comparisons.
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|
|
706 multiclass SF<bits<3> op2Val, string AsmStr> {
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|
|
707 let F = 1, Rd = R0.Num, JJJJJ = 0, Defs = [SR], DDDI = 0 in
|
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|
708 def _RR : InstRR<op2Val, (outs), (ins GPR:$Rs1, GPR:$Rs2),
|
|
|
709 !strconcat(AsmStr, "\t$Rs1, $Rs2, %r0"),
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|
|
710 [(LanaiSetFlag (i32 GPR:$Rs1), (i32 GPR:$Rs2))]>;
|
|
|
711 let F = 1, Rd = R0.Num, H = 0, Defs = [SR] in
|
|
|
712 def _RI_LO : InstRI<op2Val, (outs), (ins GPR:$Rs1, i32lo16z:$imm16),
|
|
|
713 !strconcat(AsmStr, "\t$Rs1, $imm16, %r0"),
|
|
|
714 [(LanaiSetFlag (i32 GPR:$Rs1), i32lo16z:$imm16)]>;
|
|
|
715 let F = 1, Rd = R0.Num, H = 1, Defs = [SR] in
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|
716 def _RI_HI : InstRI<op2Val, (outs), (ins GPR:$Rs1, i32hi16:$imm16),
|
|
|
717 !strconcat(AsmStr, "\t$Rs1, $imm16, %r0"),
|
|
|
718 [(LanaiSetFlag (i32 GPR:$Rs1), i32hi16:$imm16)]>;
|
|
|
719 }
|
|
|
720 let isCodeGenOnly = 1, isCompare = 1 in {
|
|
|
721 defm SFSUB_F : SF<0b010, "sub.f">;
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|
|
722 }
|
|
|
723
|
|
|
724 // Jump and link
|
|
|
725 let isCall = 1, hasDelaySlot = 1, isCodeGenOnly = 1, Uses = [SP],
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|
|
726 Defs = [RCA] in {
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|
|
727 def CALL : Pseudo<(outs), (ins CallTarget:$addr), "", []>;
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|
|
728 def CALLR : Pseudo<(outs), (ins GPR:$Rs1), "", [(Call GPR:$Rs1)]>;
|
|
|
729 }
|
|
|
730
|
|
|
731 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
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|
|
732 Uses = [RCA] in {
|
|
|
733 def RET : InstRM<0b0, (outs), (ins),
|
|
|
734 "ld\t-4[%fp], %pc ! return",
|
|
|
735 [(RetFlag)]> {
|
|
|
736 let Rd = PC.Num;
|
|
|
737 let Rs1 = FP.Num;
|
|
|
738 let P = 1;
|
|
|
739 let Q = 0;
|
|
|
740 let imm16 = -4;
|
|
|
741
|
|
|
742 // Post encoding is not needed for RET.
|
|
|
743 let PostEncoderMethod = "";
|
|
|
744 }
|
|
|
745 }
|
|
|
746
|
|
|
747 // ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into
|
|
|
748 // a stack adjustment and the codegen must know that they may modify the stack
|
|
|
749 // pointer before prolog-epilog rewriting occurs.
|
|
|
750 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
|
|
751 // sub / add which can clobber SP.
|
|
|
752 let Defs = [SP], Uses = [SP] in {
|
|
|
753 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
|
|
|
754 "#ADJCALLSTACKDOWN $amt",
|
|
|
755 [(CallSeqStart timm:$amt)]>;
|
|
|
756 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
|
|
757 "#ADJCALLSTACKUP $amt1 $amt2",
|
|
|
758 [(CallSeqEnd timm:$amt1, timm:$amt2)]>;
|
|
|
759 }
|
|
|
760
|
|
|
761 let Defs = [SP], Uses = [SP] in {
|
|
|
762 def ADJDYNALLOC : Pseudo<(outs GPR:$dst), (ins GPR:$src),
|
|
|
763 "#ADJDYNALLOC $dst $src",
|
|
|
764 [(set GPR:$dst, (LanaiAdjDynAlloc GPR:$src))]>;
|
|
|
765 }
|
|
|
766
|
|
|
767 let Uses = [SR] in {
|
|
|
768 def SCC : InstSCC<(outs GPR:$Rs1), (ins CCOp:$DDDI),
|
|
|
769 "s$DDDI\t$Rs1",
|
|
|
770 [(set (i32 GPR:$Rs1), (LanaiSetCC imm:$DDDI))]>;
|
|
|
771 }
|
|
|
772
|
|
|
773 // SCC's output is already 1-bit so and'ing with 1 is redundant.
|
|
|
774 def : Pat<(and (LanaiSetCC imm:$DDDI), 1), (SCC imm:$DDDI)>;
|
|
|
775
|
|
|
776 // Select with hardware support
|
|
|
777 let Uses = [SR], isSelect = 1 in {
|
|
|
778 def SELECT : InstRR<0b111, (outs GPR:$Rd),
|
|
|
779 (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
|
|
|
780 "sel.$DDDI $Rs1, $Rs2, $Rd",
|
|
|
781 [(set (i32 GPR:$Rd),
|
|
|
782 (LanaiSelectCC (i32 GPR:$Rs1), (i32 GPR:$Rs2),
|
|
|
783 (imm:$DDDI)))]> {
|
|
|
784 let JJJJJ = 0;
|
|
|
785 let F = 0;
|
|
|
786 }
|
|
|
787 }
|
|
|
788
|
|
|
789 let isBranch = 1, isBarrier = 1, isTerminator = 1, hasDelaySlot = 1,
|
|
|
790 isIndirectBranch = 1, Uses = [SR] in {
|
|
|
791 def BRIND_CC : InstRR<0b101, (outs), (ins GPR:$Rs1, CCOp:$DDDI),
|
|
|
792 "b$DDDI\t$Rs1", []> {
|
|
|
793 let F = 0;
|
|
|
794 let JJJJJ = 0;
|
|
|
795 let Rd = PC.Num;
|
|
|
796 let Rs2 = R0.Num;
|
|
|
797 }
|
|
|
798
|
|
|
799 def BRIND_CCA : InstRR<0b101, (outs), (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
|
|
|
800 "b${DDDI}\t$Rs1 add $Rs2", []> {
|
|
|
801 let F = 0;
|
|
|
802 let Rd = PC.Num;
|
|
|
803 let JJJJJ = 0;
|
|
|
804 }
|
|
|
805 }
|
|
|
806
|
|
|
807 // TODO: This only considers the case where BROFF is an immediate and not where
|
|
|
808 // it is a register. Add support for register relative branching.
|
|
|
809 let isBranch = 1, isBarrier = 1, isTerminator = 1, hasDelaySlot = 1, Rs1 = 0,
|
|
|
810 Uses = [SR] in
|
|
|
811 def BRR : InstBRR<(outs), (ins i16imm:$imm16, CCOp:$DDDI),
|
|
|
812 "b${DDDI}.r\t$imm16", []>;
|
|
|
813
|
|
|
814 let F = 0 in {
|
|
|
815 // Population Count (POPC)
|
|
|
816 def POPC: InstSpecial<0b001, (outs GPR:$Rd), (ins GPR:$Rs1),
|
|
|
817 "popc\t$Rs1, $Rd",
|
|
|
818 [(set GPR:$Rd, (ctpop GPR:$Rs1))]>;
|
|
|
819
|
|
|
820 // Count Leading Zeros (LEADZ)
|
|
|
821 def LEADZ: InstSpecial<0b010, (outs GPR:$Rd), (ins GPR:$Rs1),
|
|
|
822 "leadz\t$Rs1, $Rd", [(set GPR:$Rd, (ctlz GPR:$Rs1))]>;
|
|
|
823
|
|
|
824 // Count Trailing Zeros (TRAILZ)
|
|
|
825 def TRAILZ : InstSpecial<0b011, (outs GPR:$Rd), (ins GPR:$Rs1),
|
|
|
826 "trailz\t$Rs1, $Rd",
|
|
|
827 [(set GPR:$Rd, (cttz GPR:$Rs1))]>;
|
|
|
828 }
|
|
|
829
|
|
|
830 //===----------------------------------------------------------------------===//
|
|
|
831 // Non-Instruction Patterns
|
|
|
832 //===----------------------------------------------------------------------===//
|
|
|
833
|
|
|
834 // i32 0 and R0 can be used interchangeably.
|
|
|
835 def : Pat<(i32 0), (i32 R0)>;
|
|
|
836 // i32 -1 and R1 can be used interchangeably.
|
|
|
837 def : Pat<(i32 -1), (i32 R1)>;
|
|
|
838
|
|
|
839 // unsigned 16-bit immediate
|
|
|
840 def : Pat<(i32 i32lo16z:$imm), (OR_I_LO (i32 R0), imm:$imm)>;
|
|
|
841
|
|
|
842 // arbitrary immediate
|
|
|
843 def : Pat<(i32 imm:$imm), (OR_I_LO (MOVHI (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
|
|
844
|
|
|
845 // Calls
|
|
|
846 def : Pat<(Call tglobaladdr:$dst), (CALL tglobaladdr:$dst)>;
|
|
|
847 def : Pat<(Call texternalsym:$dst), (CALL texternalsym:$dst)>;
|
|
|
848
|
|
|
849 // Loads
|
|
|
850 def : Pat<(extloadi8 ADDRspls:$src), (i32 (LDBz_RI ADDRspls:$src))>;
|
|
|
851 def : Pat<(extloadi16 ADDRspls:$src), (i32 (LDHz_RI ADDRspls:$src))>;
|
|
|
852
|
|
|
853 // GlobalAddress, ExternalSymbol, Jumptable, ConstantPool
|
|
|
854 def : Pat<(LanaiHi tglobaladdr:$dst), (MOVHI tglobaladdr:$dst)>;
|
|
|
855 def : Pat<(LanaiLo tglobaladdr:$dst), (OR_I_LO (i32 R0), tglobaladdr:$dst)>;
|
|
|
856 def : Pat<(LanaiSmall tglobaladdr:$dst), (SLI tglobaladdr:$dst)>;
|
|
|
857 def : Pat<(LanaiHi texternalsym:$dst), (MOVHI texternalsym:$dst)>;
|
|
|
858 def : Pat<(LanaiLo texternalsym:$dst), (OR_I_LO (i32 R0), texternalsym:$dst)>;
|
|
|
859 def : Pat<(LanaiSmall texternalsym:$dst), (SLI texternalsym:$dst)>;
|
|
|
860 def : Pat<(LanaiHi tblockaddress:$dst), (MOVHI tblockaddress:$dst)>;
|
|
|
861 def : Pat<(LanaiLo tblockaddress:$dst), (OR_I_LO (i32 R0), tblockaddress:$dst)>;
|
|
|
862 def : Pat<(LanaiSmall tblockaddress:$dst), (SLI tblockaddress:$dst)>;
|
|
|
863 def : Pat<(LanaiHi tjumptable:$dst), (MOVHI tjumptable:$dst)>;
|
|
|
864 def : Pat<(LanaiLo tjumptable:$dst), (OR_I_LO (i32 R0), tjumptable:$dst)>;
|
|
|
865 def : Pat<(LanaiSmall tjumptable:$dst), (SLI tjumptable:$dst)>;
|
|
|
866 def : Pat<(LanaiHi tconstpool:$dst), (MOVHI tconstpool:$dst)>;
|
|
|
867 def : Pat<(LanaiLo tconstpool:$dst), (OR_I_LO (i32 R0), tconstpool:$dst)>;
|
|
|
868 def : Pat<(LanaiSmall tconstpool:$dst), (SLI tconstpool:$dst)>;
|
|
|
869
|
|
|
870 def : Pat<(or GPR:$hi, (LanaiLo tglobaladdr:$lo)),
|
|
|
871 (OR_I_LO GPR:$hi, tglobaladdr:$lo)>;
|
|
|
872 def : Pat<(or R0, (LanaiSmall tglobaladdr:$small)),
|
|
|
873 (SLI tglobaladdr:$small)>;
|
|
|
874 def : Pat<(or GPR:$hi, (LanaiLo texternalsym:$lo)),
|
|
|
875 (OR_I_LO GPR:$hi, texternalsym:$lo)>;
|
|
|
876 def : Pat<(or R0, (LanaiSmall texternalsym:$small)),
|
|
|
877 (SLI texternalsym:$small)>;
|
|
|
878 def : Pat<(or GPR:$hi, (LanaiLo tblockaddress:$lo)),
|
|
|
879 (OR_I_LO GPR:$hi, tblockaddress:$lo)>;
|
|
|
880 def : Pat<(or R0, (LanaiSmall tblockaddress:$small)),
|
|
|
881 (SLI tblockaddress:$small)>;
|
|
|
882 def : Pat<(or GPR:$hi, (LanaiLo tjumptable:$lo)),
|
|
|
883 (OR_I_LO GPR:$hi, tjumptable:$lo)>;
|
|
|
884 def : Pat<(or R0, (LanaiSmall tjumptable:$small)),
|
|
|
885 (SLI tjumptable:$small)>;
|
|
|
886 def : Pat<(or GPR:$hi, (LanaiLo tconstpool:$lo)),
|
|
|
887 (OR_I_LO GPR:$hi, tconstpool:$lo)>;
|
|
|
888 def : Pat<(or R0, (LanaiSmall tconstpool:$small)),
|
|
|
889 (SLI tconstpool:$small)>;
|
