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1 //=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the machine model for ZEC12 to support instruction
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11 // scheduling and other instruction cost heuristics.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 def ZEC12Model : SchedMachineModel {
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16
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17 let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
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18
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19 let IssueWidth = 5;
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20 let MicroOpBufferSize = 40; // Issue queues
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21 let LoadLatency = 1; // Optimistic load latency.
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22
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23 let PostRAScheduler = 1;
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24
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25 // Extra cycles for a mispredicted branch.
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26 let MispredictPenalty = 8;
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27 }
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28
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29 let SchedModel = ZEC12Model in {
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30
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31 // These definitions could be put in a subtarget common include file,
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32 // but it seems the include system in Tablegen currently rejects
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33 // multiple includes of same file.
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34 def : WriteRes<GroupAlone, []> {
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35 let NumMicroOps = 0;
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36 let BeginGroup = 1;
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37 let EndGroup = 1;
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38 }
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39 def : WriteRes<EndGroup, []> {
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40 let NumMicroOps = 0;
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41 let EndGroup = 1;
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42 }
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43 def : WriteRes<Lat2, []> { let Latency = 2; let NumMicroOps = 0;}
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44 def : WriteRes<Lat3, []> { let Latency = 3; let NumMicroOps = 0;}
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45 def : WriteRes<Lat4, []> { let Latency = 4; let NumMicroOps = 0;}
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46 def : WriteRes<Lat5, []> { let Latency = 5; let NumMicroOps = 0;}
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47 def : WriteRes<Lat6, []> { let Latency = 6; let NumMicroOps = 0;}
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48 def : WriteRes<Lat7, []> { let Latency = 7; let NumMicroOps = 0;}
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49 def : WriteRes<Lat8, []> { let Latency = 8; let NumMicroOps = 0;}
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50 def : WriteRes<Lat9, []> { let Latency = 9; let NumMicroOps = 0;}
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51 def : WriteRes<Lat10, []> { let Latency = 10; let NumMicroOps = 0;}
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52 def : WriteRes<Lat11, []> { let Latency = 11; let NumMicroOps = 0;}
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53 def : WriteRes<Lat12, []> { let Latency = 12; let NumMicroOps = 0;}
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54 def : WriteRes<Lat15, []> { let Latency = 15; let NumMicroOps = 0;}
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55 def : WriteRes<Lat20, []> { let Latency = 20; let NumMicroOps = 0;}
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56 def : WriteRes<Lat30, []> { let Latency = 30; let NumMicroOps = 0;}
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57
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58 // Execution units.
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59 def ZEC12_FXUnit : ProcResource<2>;
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60 def ZEC12_LSUnit : ProcResource<2>;
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61 def ZEC12_FPUnit : ProcResource<1>;
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62 def ZEC12_VBUnit : ProcResource<1>;
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63
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64 // Subtarget specific definitions of scheduling resources.
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65 def : WriteRes<FXU, [ZEC12_FXUnit]> { let Latency = 1; }
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66 def : WriteRes<LSU, [ZEC12_LSUnit]> { let Latency = 4; }
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67 def : WriteRes<LSU_lat1, [ZEC12_LSUnit]> { let Latency = 1; }
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68 def : WriteRes<FPU, [ZEC12_FPUnit]> { let Latency = 8; }
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69 def : WriteRes<FPU2, [ZEC12_FPUnit, ZEC12_FPUnit]> { let Latency = 9; }
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70 def : WriteRes<VBU, [ZEC12_VBUnit]>; // Virtual Branching Unit
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71
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72 // -------------------------- INSTRUCTIONS ---------------------------------- //
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73
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74 // InstRW constructs have been used in order to preserve the
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75 // readability of the InstrInfo files.
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76
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77 // For each instruction, as matched by a regexp, provide a list of
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78 // resources that it needs. These will be combined into a SchedClass.
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79
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80 //===----------------------------------------------------------------------===//
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81 // Stack allocation
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82 //===----------------------------------------------------------------------===//
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83
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84 def : InstRW<[FXU], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
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85
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86 //===----------------------------------------------------------------------===//
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87 // Branch instructions
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88 //===----------------------------------------------------------------------===//
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89
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90 // Branch
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91 def : InstRW<[VBU], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
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92 def : InstRW<[VBU], (instregex "(Call)?J(G)?(Asm.*)?$")>;
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93 def : InstRW<[LSU, Lat4], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
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94 def : InstRW<[LSU, Lat4], (instregex "(Call)?B(R)?(Asm.*)?$")>;
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95 def : InstRW<[FXU, EndGroup], (instregex "BRCT(G)?$")>;
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96 def : InstRW<[FXU, FXU, FXU, LSU, Lat7, GroupAlone], (instregex "BRX(H|LE)$")>;
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97
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98 // Compare and branch
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99 def : InstRW<[FXU], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
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100 def : InstRW<[FXU, LSU, Lat5, GroupAlone],
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101 (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
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102
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103 //===----------------------------------------------------------------------===//
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104 // Trap instructions
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105 //===----------------------------------------------------------------------===//
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106
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107 // Trap
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108 def : InstRW<[VBU], (instregex "(Cond)?Trap$")>;
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109
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110 // Compare and trap
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111 def : InstRW<[FXU], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
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112 def : InstRW<[FXU], (instregex "CL(G)?RT(Asm.*)?$")>;
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113 def : InstRW<[FXU], (instregex "CL(F|G)IT(Asm.*)?$")>;
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114 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(G)?T(Asm.*)?$")>;
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115
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116 //===----------------------------------------------------------------------===//
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117 // Call and return instructions
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118 //===----------------------------------------------------------------------===//
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119
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120 // Call
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121 def : InstRW<[VBU, FXU, FXU, Lat3, GroupAlone], (instregex "(Call)?BRAS$")>;
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122 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BRASL$")>;
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123 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
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124 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
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125
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126 // Return
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127 def : InstRW<[LSU_lat1, EndGroup], (instregex "Return$")>;
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128 def : InstRW<[LSU_lat1], (instregex "CondReturn$")>;
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129
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130 //===----------------------------------------------------------------------===//
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131 // Select instructions
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132 //===----------------------------------------------------------------------===//
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133
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134 // Select pseudo
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135 def : InstRW<[FXU], (instregex "Select(32|64|32Mux)$")>;
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136
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137 // CondStore pseudos
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138 def : InstRW<[FXU], (instregex "CondStore16(Inv)?$")>;
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139 def : InstRW<[FXU], (instregex "CondStore16Mux(Inv)?$")>;
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140 def : InstRW<[FXU], (instregex "CondStore32(Inv)?$")>;
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141 def : InstRW<[FXU], (instregex "CondStore64(Inv)?$")>;
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142 def : InstRW<[FXU], (instregex "CondStore8(Inv)?$")>;
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143 def : InstRW<[FXU], (instregex "CondStore8Mux(Inv)?$")>;
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144
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145 //===----------------------------------------------------------------------===//
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146 // Move instructions
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147 //===----------------------------------------------------------------------===//
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148
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149 // Moves
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150 def : InstRW<[FXU, LSU, Lat5], (instregex "MV(G|H)?HI$")>;
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151 def : InstRW<[FXU, LSU, Lat5], (instregex "MVI(Y)?$")>;
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152
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153 // Move character
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154 def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
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155
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156 // Pseudo -> reg move
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157 def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
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158 def : InstRW<[FXU], (instregex "EXTRACT_SUBREG$")>;
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159 def : InstRW<[FXU], (instregex "INSERT_SUBREG$")>;
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160 def : InstRW<[FXU], (instregex "REG_SEQUENCE$")>;
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161 def : InstRW<[FXU], (instregex "SUBREG_TO_REG$")>;
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162
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163 // Loads
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164 def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux)?$")>;
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165 def : InstRW<[LSU], (instregex "LG(RL)?$")>;
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166 def : InstRW<[LSU], (instregex "L128$")>;
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167
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168 def : InstRW<[FXU], (instregex "LLIH(F|H|L)$")>;
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169 def : InstRW<[FXU], (instregex "LLIL(F|H|L)$")>;
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170
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171 def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
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172 def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
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173 def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
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174
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175 // Load and test
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176 def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
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177 def : InstRW<[FXU], (instregex "LT(G)?R$")>;
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178
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179 // Stores
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180 def : InstRW<[FXU, LSU, Lat5], (instregex "STG(RL)?$")>;
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181 def : InstRW<[FXU, LSU, Lat5], (instregex "ST128$")>;
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182 def : InstRW<[FXU, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>;
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183
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184 // String moves.
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185 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>;
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186
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187 //===----------------------------------------------------------------------===//
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188 // Conditional move instructions
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189 //===----------------------------------------------------------------------===//
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190
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191 def : InstRW<[FXU, Lat2], (instregex "LOC(G)?R(Asm.*)?$")>;
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192 def : InstRW<[FXU, Lat2], (instregex "LOC(G)?HI(Asm.*)?$")>;
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193 def : InstRW<[FXU, LSU, Lat6], (instregex "LOC(G)?(Asm.*)?$")>;
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194 def : InstRW<[FXU, LSU, Lat5], (instregex "STOC(G)?(Asm.*)?$")>;
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195
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196 //===----------------------------------------------------------------------===//
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197 // Sign extensions
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198 //===----------------------------------------------------------------------===//
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199
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200 def : InstRW<[FXU], (instregex "L(B|H|G)R$")>;
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201 def : InstRW<[FXU], (instregex "LG(B|H|F)R$")>;
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202
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203 def : InstRW<[FXU, LSU, Lat5], (instregex "LTGF$")>;
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204 def : InstRW<[FXU], (instregex "LTGFR$")>;
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205
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206 def : InstRW<[FXU, LSU, Lat5], (instregex "LB(H|Mux)?$")>;
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207 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(Y)?$")>;
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208 def : InstRW<[FXU, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>;
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209 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(B|H|F)$")>;
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210 def : InstRW<[FXU, LSU, Lat5], (instregex "LG(H|F)RL$")>;
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211
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212 //===----------------------------------------------------------------------===//
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213 // Zero extensions
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214 //===----------------------------------------------------------------------===//
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215
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216 def : InstRW<[FXU], (instregex "LLCR(Mux)?$")>;
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217 def : InstRW<[FXU], (instregex "LLHR(Mux)?$")>;
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218 def : InstRW<[FXU], (instregex "LLG(C|H|F|T)R$")>;
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219 def : InstRW<[LSU], (instregex "LLC(Mux)?$")>;
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220 def : InstRW<[LSU], (instregex "LLH(Mux)?$")>;
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221 def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
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222 def : InstRW<[LSU], (instregex "LLHRL$")>;
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223 def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
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224
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225 //===----------------------------------------------------------------------===//
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226 // Truncations
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227 //===----------------------------------------------------------------------===//
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228
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229 def : InstRW<[FXU, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>;
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230 def : InstRW<[FXU, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>;
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231
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232 //===----------------------------------------------------------------------===//
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233 // Multi-register moves
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234 //===----------------------------------------------------------------------===//
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235
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236 // Load multiple (estimated average of 5 ops)
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237 def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone],
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238 (instregex "LM(H|Y|G)?$")>;
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239
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240 // Store multiple (estimated average of 3 ops)
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241 def : InstRW<[LSU, LSU, FXU, FXU, FXU, Lat10, GroupAlone],
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242 (instregex "STM(H|Y|G)?$")>;
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243
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244 //===----------------------------------------------------------------------===//
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245 // Byte swaps
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246 //===----------------------------------------------------------------------===//
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247
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248 def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
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249 def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
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250 def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
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251
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252 //===----------------------------------------------------------------------===//
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253 // Load address instructions
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254 //===----------------------------------------------------------------------===//
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255
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256 def : InstRW<[FXU], (instregex "LA(Y|RL)?$")>;
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257
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258 // Load the Global Offset Table address
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259 def : InstRW<[FXU], (instregex "GOT$")>;
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260
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261 //===----------------------------------------------------------------------===//
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262 // Absolute and Negation
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263 //===----------------------------------------------------------------------===//
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264
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265 def : InstRW<[FXU, Lat2], (instregex "LP(G)?R$")>;
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266 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "L(N|P)GFR$")>;
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267 def : InstRW<[FXU, Lat2], (instregex "LN(R|GR)$")>;
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268 def : InstRW<[FXU], (instregex "LC(R|GR)$")>;
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269 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LCGFR$")>;
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270
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271 //===----------------------------------------------------------------------===//
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272 // Insertion
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273 //===----------------------------------------------------------------------===//
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274
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275 def : InstRW<[FXU, LSU, Lat5], (instregex "IC(Y)?$")>;
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276 def : InstRW<[FXU, LSU, Lat5], (instregex "IC32(Y)?$")>;
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277 def : InstRW<[FXU, LSU, Lat5], (instregex "ICM(H|Y)?$")>;
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278 def : InstRW<[FXU], (instregex "II(F|H|L)Mux$")>;
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279 def : InstRW<[FXU], (instregex "IIHF(64)?$")>;
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280 def : InstRW<[FXU], (instregex "IIHH(64)?$")>;
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281 def : InstRW<[FXU], (instregex "IIHL(64)?$")>;
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282 def : InstRW<[FXU], (instregex "IILF(64)?$")>;
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283 def : InstRW<[FXU], (instregex "IILH(64)?$")>;
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284 def : InstRW<[FXU], (instregex "IILL(64)?$")>;
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285
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286 //===----------------------------------------------------------------------===//
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287 // Addition
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288 //===----------------------------------------------------------------------===//
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289
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290 def : InstRW<[FXU, LSU, Lat5], (instregex "A(Y|SI)?$")>;
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291 def : InstRW<[FXU, LSU, Lat6], (instregex "AH(Y)?$")>;
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292 def : InstRW<[FXU], (instregex "AIH$")>;
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293 def : InstRW<[FXU], (instregex "AFI(Mux)?$")>;
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294 def : InstRW<[FXU], (instregex "AGFI$")>;
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295 def : InstRW<[FXU], (instregex "AGHI(K)?$")>;
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296 def : InstRW<[FXU], (instregex "AGR(K)?$")>;
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297 def : InstRW<[FXU], (instregex "AHI(K)?$")>;
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298 def : InstRW<[FXU], (instregex "AHIMux(K)?$")>;
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299 def : InstRW<[FXU, LSU, Lat5], (instregex "AL(Y)?$")>;
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300 def : InstRW<[FXU], (instregex "AL(FI|HSIK)$")>;
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301 def : InstRW<[FXU, LSU, Lat5], (instregex "ALG(F)?$")>;
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302 def : InstRW<[FXU], (instregex "ALGHSIK$")>;
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303 def : InstRW<[FXU], (instregex "ALGF(I|R)$")>;
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304 def : InstRW<[FXU], (instregex "ALGR(K)?$")>;
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305 def : InstRW<[FXU], (instregex "ALR(K)?$")>;
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306 def : InstRW<[FXU], (instregex "AR(K)?$")>;
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307 def : InstRW<[FXU, LSU, Lat5], (instregex "AG(SI)?$")>;
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308
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309 // Logical addition with carry
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310 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "ALC(G)?$")>;
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311 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "ALC(G)?R$")>;
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312
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313 // Add with sign extension (32 -> 64)
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314 def : InstRW<[FXU, LSU, Lat6], (instregex "AGF$")>;
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315 def : InstRW<[FXU, Lat2], (instregex "AGFR$")>;
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316
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317 //===----------------------------------------------------------------------===//
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318 // Subtraction
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319 //===----------------------------------------------------------------------===//
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320
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321 def : InstRW<[FXU, LSU, Lat5], (instregex "S(G|Y)?$")>;
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322 def : InstRW<[FXU, LSU, Lat6], (instregex "SH(Y)?$")>;
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323 def : InstRW<[FXU], (instregex "SGR(K)?$")>;
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324 def : InstRW<[FXU], (instregex "SLFI$")>;
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325 def : InstRW<[FXU, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>;
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|
326 def : InstRW<[FXU], (instregex "SLGF(I|R)$")>;
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327 def : InstRW<[FXU], (instregex "SLGR(K)?$")>;
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328 def : InstRW<[FXU], (instregex "SLR(K)?$")>;
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329 def : InstRW<[FXU], (instregex "SR(K)?$")>;
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330
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331 // Subtraction with borrow
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332 def : InstRW<[FXU, LSU, Lat7, GroupAlone], (instregex "SLB(G)?$")>;
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333 def : InstRW<[FXU, Lat3, GroupAlone], (instregex "SLB(G)?R$")>;
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334
|
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|
335 // Subtraction with sign extension (32 -> 64)
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336 def : InstRW<[FXU, LSU, Lat6], (instregex "SGF$")>;
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337 def : InstRW<[FXU, Lat2], (instregex "SGFR$")>;
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338
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|
339 //===----------------------------------------------------------------------===//
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|
340 // AND
|
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|
341 //===----------------------------------------------------------------------===//
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342
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343 def : InstRW<[FXU, LSU, Lat5], (instregex "N(G|Y)?$")>;
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344 def : InstRW<[FXU], (instregex "NGR(K)?$")>;
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345 def : InstRW<[FXU], (instregex "NI(FMux|HMux|LMux)$")>;
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346 def : InstRW<[FXU, LSU, Lat5], (instregex "NI(Y)?$")>;
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347 def : InstRW<[FXU], (instregex "NIHF(64)?$")>;
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348 def : InstRW<[FXU], (instregex "NIHH(64)?$")>;
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349 def : InstRW<[FXU], (instregex "NIHL(64)?$")>;
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350 def : InstRW<[FXU], (instregex "NILF(64)?$")>;
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351 def : InstRW<[FXU], (instregex "NILH(64)?$")>;
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352 def : InstRW<[FXU], (instregex "NILL(64)?$")>;
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353 def : InstRW<[FXU], (instregex "NR(K)?$")>;
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354 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "NC$")>;
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355
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356 //===----------------------------------------------------------------------===//
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357 // OR
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358 //===----------------------------------------------------------------------===//
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359
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360 def : InstRW<[FXU, LSU, Lat5], (instregex "O(G|Y)?$")>;
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361 def : InstRW<[FXU], (instregex "OGR(K)?$")>;
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362 def : InstRW<[FXU, LSU, Lat5], (instregex "OI(Y)?$")>;
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363 def : InstRW<[FXU], (instregex "OI(FMux|HMux|LMux)$")>;
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364 def : InstRW<[FXU], (instregex "OIHF(64)?$")>;
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365 def : InstRW<[FXU], (instregex "OIHH(64)?$")>;
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366 def : InstRW<[FXU], (instregex "OIHL(64)?$")>;
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367 def : InstRW<[FXU], (instregex "OILF(64)?$")>;
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368 def : InstRW<[FXU], (instregex "OILH(64)?$")>;
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369 def : InstRW<[FXU], (instregex "OILL(64)?$")>;
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370 def : InstRW<[FXU], (instregex "OR(K)?$")>;
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|
371 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "OC$")>;
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372
|
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|
373 //===----------------------------------------------------------------------===//
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|
374 // XOR
|
|
|
375 //===----------------------------------------------------------------------===//
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376
|
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377 def : InstRW<[FXU, LSU, Lat5], (instregex "X(G|Y)?$")>;
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378 def : InstRW<[FXU, LSU, Lat5], (instregex "XI(Y)?$")>;
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379 def : InstRW<[FXU], (instregex "XIFMux$")>;
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380 def : InstRW<[FXU], (instregex "XGR(K)?$")>;
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|
381 def : InstRW<[FXU], (instregex "XIHF(64)?$")>;
|
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|
382 def : InstRW<[FXU], (instregex "XILF(64)?$")>;
|
|
|
383 def : InstRW<[FXU], (instregex "XR(K)?$")>;
|
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|
384 def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "XC$")>;
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385
|
|
|
386 //===----------------------------------------------------------------------===//
|
|
|
387 // Multiplication
|
|
|
388 //===----------------------------------------------------------------------===//
|
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|
389
|
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|
390 def : InstRW<[FXU, LSU, Lat10], (instregex "MS(GF|Y)?$")>;
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|
391 def : InstRW<[FXU, Lat6], (instregex "MS(R|FI)$")>;
|
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|
392 def : InstRW<[FXU, LSU, Lat12], (instregex "MSG$")>;
|
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|
393 def : InstRW<[FXU, Lat8], (instregex "MSGR$")>;
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|
394 def : InstRW<[FXU, Lat6], (instregex "MSGF(I|R)$")>;
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|
395 def : InstRW<[FXU, LSU, Lat15, GroupAlone], (instregex "MLG$")>;
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|
396 def : InstRW<[FXU, Lat9, GroupAlone], (instregex "MLGR$")>;
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|
397 def : InstRW<[FXU, Lat5], (instregex "MGHI$")>;
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|
398 def : InstRW<[FXU, Lat5], (instregex "MHI$")>;
|
|
|
399 def : InstRW<[FXU, LSU, Lat9], (instregex "MH(Y)?$")>;
|
|
|
400
|
|
|
401 //===----------------------------------------------------------------------===//
|
|
|
402 // Division and remainder
|
|
|
403 //===----------------------------------------------------------------------===//
|
|
|
404
|
|
|
405 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
|
406 (instregex "DSG(F)?R$")>;
|
|
|
407 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
|
408 (instregex "DSG(F)?$")>;
|
|
|
409 def : InstRW<[FPU2, FPU2, FXU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
|
410 (instregex "DL(G)?R$")>;
|
|
|
411 def : InstRW<[FPU2, FPU2, LSU, FXU, FXU, FXU, FXU, Lat30, GroupAlone],
|
|
|
412 (instregex "DL(G)?$")>;
|
|
|
413
|
|
|
414 //===----------------------------------------------------------------------===//
|
|
|
415 // Shifts
|
|
|
416 //===----------------------------------------------------------------------===//
|
|
|
417
|
|
|
418 def : InstRW<[FXU], (instregex "SLL(G|K)?$")>;
|
|
|
419 def : InstRW<[FXU], (instregex "SRL(G|K)?$")>;
|
|
|
420 def : InstRW<[FXU], (instregex "SRA(G|K)?$")>;
|
|
|
421 def : InstRW<[FXU], (instregex "SLA(K)?$")>;
|
|
|
422
|
|
|
423 // Rotate
|
|
|
424 def : InstRW<[FXU, LSU, Lat6], (instregex "RLL(G)?$")>;
|
|
|
425
|
|
|
426 // Rotate and insert
|
|
|
427 def : InstRW<[FXU], (instregex "RISBG(N|32)?$")>;
|
|
|
428 def : InstRW<[FXU], (instregex "RISBH(G|H|L)$")>;
|
|
|
429 def : InstRW<[FXU], (instregex "RISBL(G|H|L)$")>;
|
|
|
430 def : InstRW<[FXU], (instregex "RISBMux$")>;
|
|
|
431
|
|
|
432 // Rotate and Select
|
|
|
433 def : InstRW<[FXU, FXU, Lat3, GroupAlone], (instregex "R(N|O|X)SBG$")>;
|
|
|
434
|
|
|
435 //===----------------------------------------------------------------------===//
|
|
|
436 // Comparison
|
|
|
437 //===----------------------------------------------------------------------===//
|
|
|
438
|
|
|
439 def : InstRW<[FXU, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>;
|
|
|
440 def : InstRW<[FXU], (instregex "CFI(Mux)?$")>;
|
|
|
441 def : InstRW<[FXU], (instregex "CG(F|H)I$")>;
|
|
|
442 def : InstRW<[FXU, LSU, Lat5], (instregex "CG(HSI|RL)$")>;
|
|
|
443 def : InstRW<[FXU], (instregex "C(G)?R$")>;
|
|
|
444 def : InstRW<[FXU], (instregex "C(HI|IH)$")>;
|
|
|
445 def : InstRW<[FXU, LSU, Lat5], (instregex "CH(F|SI)$")>;
|
|
|
446 def : InstRW<[FXU, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>;
|
|
|
447 def : InstRW<[FXU], (instregex "CLFI(Mux)?$")>;
|
|
|
448 def : InstRW<[FXU, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>;
|
|
|
449 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGF(RL)?$")>;
|
|
|
450 def : InstRW<[FXU], (instregex "CLGF(I|R)$")>;
|
|
|
451 def : InstRW<[FXU], (instregex "CLGR$")>;
|
|
|
452 def : InstRW<[FXU, LSU, Lat5], (instregex "CLGRL$")>;
|
|
|
453 def : InstRW<[FXU, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>;
|
|
|
454 def : InstRW<[FXU], (instregex "CLIH$")>;
|
|
|
455 def : InstRW<[FXU, LSU, Lat5], (instregex "CLI(Y)?$")>;
|
|
|
456 def : InstRW<[FXU], (instregex "CLR$")>;
|
|
|
457 def : InstRW<[FXU, LSU, Lat5], (instregex "CLRL$")>;
|
|
|
458
|
|
|
459 // Compare halfword
|
|
|
460 def : InstRW<[FXU, LSU, Lat6], (instregex "CH(Y|RL)?$")>;
|
|
|
461 def : InstRW<[FXU, LSU, Lat6], (instregex "CGH(RL)?$")>;
|
|
|
462 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CHHSI$")>;
|
|
|
463
|
|
|
464 // Compare with sign extension (32 -> 64)
|
|
|
465 def : InstRW<[FXU, LSU, Lat6], (instregex "CGF(RL)?$")>;
|
|
|
466 def : InstRW<[FXU, Lat2], (instregex "CGFR$")>;
|
|
|
467
|
|
|
468 // Compare logical character
|
|
|
469 def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "CLC$")>;
|
|
|
470
|
|
|
471 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
|
|
|
472
|
|
|
473 // Test under mask
|
|
|
474 def : InstRW<[FXU, LSU, Lat5], (instregex "TM(Y)?$")>;
|
|
|
475 def : InstRW<[FXU], (instregex "TM(H|L)Mux$")>;
|
|
|
476 def : InstRW<[FXU], (instregex "TMHH(64)?$")>;
|
|
|
477 def : InstRW<[FXU], (instregex "TMHL(64)?$")>;
|
|
|
478 def : InstRW<[FXU], (instregex "TMLH(64)?$")>;
|
|
|
479 def : InstRW<[FXU], (instregex "TMLL(64)?$")>;
|
|
|
480
|
|
|
481 //===----------------------------------------------------------------------===//
|
|
|
482 // Prefetch
|
|
|
483 //===----------------------------------------------------------------------===//
|
|
|
484
|
|
|
485 def : InstRW<[LSU], (instregex "PFD(RL)?$")>;
|
|
|
486
|
|
|
487 //===----------------------------------------------------------------------===//
|
|
|
488 // Atomic operations
|
|
|
489 //===----------------------------------------------------------------------===//
|
|
|
490
|
|
|
491 def : InstRW<[LSU, EndGroup], (instregex "Serialize$")>;
|
|
|
492
|
|
|
493 def : InstRW<[FXU, LSU, Lat5], (instregex "LAA(G)?$")>;
|
|
|
494 def : InstRW<[FXU, LSU, Lat5], (instregex "LAAL(G)?$")>;
|
|
|
495 def : InstRW<[FXU, LSU, Lat5], (instregex "LAN(G)?$")>;
|
|
|
496 def : InstRW<[FXU, LSU, Lat5], (instregex "LAO(G)?$")>;
|
|
|
497 def : InstRW<[FXU, LSU, Lat5], (instregex "LAX(G)?$")>;
|
|
|
498
|
|
|
499 // Compare and swap
|
|
|
500 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
|
|
|
501
|
|
|
502 //===----------------------------------------------------------------------===//
|
|
|
503 // Access registers
|
|
|
504 //===----------------------------------------------------------------------===//
|
|
|
505
|
|
|
506 // Extract/set/copy access register
|
|
|
507 def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
|
|
|
508
|
|
|
509 // Load address extended
|
|
|
510 def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
|
|
|
511
|
|
|
512 // Load/store access multiple (not modeled precisely)
|
|
|
513 def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
|
|
|
514
|
|
|
515 //===----------------------------------------------------------------------===//
|
|
|
516 // Program mask and addressing mode
|
|
|
517 //===----------------------------------------------------------------------===//
|
|
|
518
|
|
|
519 // Insert Program Mask
|
|
|
520 def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>;
|
|
|
521
|
|
|
522 // Set Program Mask
|
|
|
523 def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
|
|
|
524
|
|
|
525 // Branch and link
|
|
|
526 def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
|
|
|
527
|
|
|
528 // Test addressing mode
|
|
|
529 def : InstRW<[FXU], (instregex "TAM$")>;
|
|
|
530
|
|
|
531 // Set addressing mode
|
|
|
532 def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
|
|
|
533
|
|
|
534 // Branch (and save) and set mode.
|
|
|
535 def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
|
|
|
536 def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
|
|
|
537
|
|
|
538 //===----------------------------------------------------------------------===//
|
|
|
539 // Transactional execution
|
|
|
540 //===----------------------------------------------------------------------===//
|
|
|
541
|
|
|
542 // Transaction begin
|
|
|
543 def : InstRW<[LSU, LSU, FXU, FXU, FXU, FXU, FXU, Lat15, GroupAlone],
|
|
|
544 (instregex "TBEGIN(C|_nofloat)?$")>;
|
|
|
545
|
|
|
546 // Transaction end
|
|
|
547 def : InstRW<[LSU, GroupAlone], (instregex "TEND$")>;
|
|
|
548
|
|
|
549 // Transaction abort
|
|
|
550 def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>;
|
|
|
551
|
|
|
552 // Extract Transaction Nesting Depth
|
|
|
553 def : InstRW<[FXU], (instregex "ETND$")>;
|
|
|
554
|
|
|
555 // Nontransactional store
|
|
|
556 def : InstRW<[FXU, LSU, Lat5], (instregex "NTSTG$")>;
|
|
|
557
|
|
|
558 //===----------------------------------------------------------------------===//
|
|
|
559 // Processor assist
|
|
|
560 //===----------------------------------------------------------------------===//
|
|
|
561
|
|
|
562 def : InstRW<[FXU], (instregex "PPA$")>;
|
|
|
563
|
|
|
564 //===----------------------------------------------------------------------===//
|
|
|
565 // Miscellaneous Instructions.
|
|
|
566 //===----------------------------------------------------------------------===//
|
|
|
567
|
|
|
568 // Find leftmost one
|
|
|
569 def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
|
|
|
570
|
|
|
571 // Population count
|
|
|
572 def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
|
|
|
573
|
|
|
574 // Extend
|
|
|
575 def : InstRW<[FXU], (instregex "AEXT128_64$")>;
|
|
|
576 def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
|
|
|
577
|
|
|
578 // String instructions
|
|
|
579 def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
|
|
|
580
|
|
|
581 // Move with key
|
|
|
582 def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
|
|
|
583
|
|
|
584 // Extract CPU Time
|
|
|
585 def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
|
|
|
586
|
|
|
587 // Execute
|
|
|
588 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
|
|
|
589
|
|
|
590 // Program return
|
|
|
591 def : InstRW<[FXU, Lat30], (instregex "PR$")>;
|
|
|
592
|
|
|
593 // Inline assembly
|
|
|
594 def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "STCK(F)?$")>;
|
|
|
595 def : InstRW<[LSU, LSU, LSU, LSU, FXU, FXU, Lat20, GroupAlone],
|
|
|
596 (instregex "STCKE$")>;
|
|
|
597 def : InstRW<[FXU, LSU, Lat5], (instregex "STFLE$")>;
|
|
|
598 def : InstRW<[FXU, Lat30], (instregex "SVC$")>;
|
|
|
599
|
|
|
600 // Store real address
|
|
|
601 def : InstRW<[FXU, LSU, Lat5], (instregex "STRAG$")>;
|
|
|
602
|
|
|
603 //===----------------------------------------------------------------------===//
|
|
|
604 // .insn directive instructions
|
|
|
605 //===----------------------------------------------------------------------===//
|
|
|
606
|
|
|
607 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
|
|
|
608 // getNumDecoderSlots() will then return 1 instead of 0.
|
|
|
609 def : InstRW<[], (instregex "Insn.*")>;
|
|
|
610
|
|
|
611
|
|
|
612 // ----------------------------- Floating point ----------------------------- //
|
|
|
613
|
|
|
614 //===----------------------------------------------------------------------===//
|
|
|
615 // FP: Select instructions
|
|
|
616 //===----------------------------------------------------------------------===//
|
|
|
617
|
|
|
618 def : InstRW<[FXU], (instregex "SelectF(32|64|128)$")>;
|
|
|
619 def : InstRW<[FXU], (instregex "CondStoreF32(Inv)?$")>;
|
|
|
620 def : InstRW<[FXU], (instregex "CondStoreF64(Inv)?$")>;
|
|
|
621
|
|
|
622 //===----------------------------------------------------------------------===//
|
|
|
623 // FP: Move instructions
|
|
|
624 //===----------------------------------------------------------------------===//
|
|
|
625
|
|
|
626 // Load zero
|
|
|
627 def : InstRW<[FXU], (instregex "LZ(DR|ER)$")>;
|
|
|
628 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LZXR$")>;
|
|
|
629
|
|
|
630 // Load
|
|
|
631 def : InstRW<[FXU], (instregex "LER$")>;
|
|
|
632 def : InstRW<[FXU], (instregex "LD(R|R32|GR)$")>;
|
|
|
633 def : InstRW<[FXU, Lat3], (instregex "LGDR$")>;
|
|
|
634 def : InstRW<[FXU, FXU, Lat2, GroupAlone], (instregex "LXR$")>;
|
|
|
635
|
|
|
636 // Load and Test
|
|
|
637 def : InstRW<[FPU], (instregex "LT(D|E)BR$")>;
|
|
|
638 def : InstRW<[FPU], (instregex "LTEBRCompare(_VecPseudo)?$")>;
|
|
|
639 def : InstRW<[FPU], (instregex "LTDBRCompare(_VecPseudo)?$")>;
|
|
|
640 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "LTXBR$")>;
|
|
|
641 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone],
|
|
|
642 (instregex "LTXBRCompare(_VecPseudo)?$")>;
|
|
|
643
|
|
|
644 // Copy sign
|
|
|
645 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRd(d|s)$")>;
|
|
|
646 def : InstRW<[FXU, FXU, Lat5, GroupAlone], (instregex "CPSDRs(d|s)$")>;
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|
|
647
|
|
|
648 //===----------------------------------------------------------------------===//
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|
|
649 // FP: Load instructions
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|
|
650 //===----------------------------------------------------------------------===//
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|
|
651
|
|
|
652 def : InstRW<[LSU], (instregex "LE(Y)?$")>;
|
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653 def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>;
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|
|
654 def : InstRW<[LSU], (instregex "LX$")>;
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|
|
655
|
|
|
656 //===----------------------------------------------------------------------===//
|
|
|
657 // FP: Store instructions
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|
|
658 //===----------------------------------------------------------------------===//
|
|
|
659
|
|
|
660 def : InstRW<[FXU, LSU, Lat7], (instregex "STD(Y)?$")>;
|
|
|
661 def : InstRW<[FXU, LSU, Lat7], (instregex "STE(Y)?$")>;
|
|
|
662 def : InstRW<[FXU, LSU, Lat5], (instregex "STX$")>;
|
|
|
663
|
|
|
664 //===----------------------------------------------------------------------===//
|
|
|
665 // FP: Conversion instructions
|
|
|
666 //===----------------------------------------------------------------------===//
|
|
|
667
|
|
|
668 // Load rounded
|
|
|
669 def : InstRW<[FPU], (instregex "LEDBR(A)?$")>;
|
|
|
670 def : InstRW<[FPU, FPU, Lat20], (instregex "LEXBR(A)?$")>;
|
|
|
671 def : InstRW<[FPU, FPU, Lat20], (instregex "LDXBR(A)?$")>;
|
|
|
672
|
|
|
673 // Load lengthened
|
|
|
674 def : InstRW<[FPU, LSU, Lat12], (instregex "LDEB$")>;
|
|
|
675 def : InstRW<[FPU], (instregex "LDEBR$")>;
|
|
|
676 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "LX(D|E)B$")>;
|
|
|
677 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "LX(D|E)BR$")>;
|
|
|
678
|
|
|
679 // Convert from fixed / logical
|
|
|
680 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CE(F|G)BR(A?)$")>;
|
|
|
681 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CD(F|G)BR(A?)$")>;
|
|
|
682 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CX(F|G)BR(A?)$")>;
|
|
|
683 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CEL(F|G)BR$")>;
|
|
|
684 def : InstRW<[FXU, FPU, Lat9, GroupAlone], (instregex "CDL(F|G)BR$")>;
|
|
|
685 def : InstRW<[FXU, FPU2, FPU2, Lat11, GroupAlone], (instregex "CXL(F|G)BR$")>;
|
|
|
686
|
|
|
687 // Convert to fixed / logical
|
|
|
688 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CF(E|D)BR(A?)$")>;
|
|
|
689 def : InstRW<[FXU, FPU, Lat12, GroupAlone], (instregex "CG(E|D)BR(A?)$")>;
|
|
|
690 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "C(F|G)XBR(A?)$")>;
|
|
|
691 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLF(E|D)BR$")>;
|
|
|
692 def : InstRW<[FXU, FPU, Lat11, GroupAlone], (instregex "CLG(E|D)BR$")>;
|
|
|
693 def : InstRW<[FXU, FPU, FPU, Lat20, GroupAlone], (instregex "CL(F|G)XBR$")>;
|
|
|
694
|
|
|
695 //===----------------------------------------------------------------------===//
|
|
|
696 // FP: Unary arithmetic
|
|
|
697 //===----------------------------------------------------------------------===//
|
|
|
698
|
|
|
699 // Load Complement / Negative / Positive
|
|
|
700 def : InstRW<[FPU], (instregex "L(C|N|P)DBR$")>;
|
|
|
701 def : InstRW<[FPU], (instregex "L(C|N|P)EBR$")>;
|
|
|
702 def : InstRW<[FXU], (instregex "LCDFR(_32)?$")>;
|
|
|
703 def : InstRW<[FXU], (instregex "LNDFR(_32)?$")>;
|
|
|
704 def : InstRW<[FXU], (instregex "LPDFR(_32)?$")>;
|
|
|
705 def : InstRW<[FPU2, FPU2, Lat9, GroupAlone], (instregex "L(C|N|P)XBR$")>;
|
|
|
706
|
|
|
707 // Square root
|
|
|
708 def : InstRW<[FPU, LSU, Lat30], (instregex "SQ(E|D)B$")>;
|
|
|
709 def : InstRW<[FPU, Lat30], (instregex "SQ(E|D)BR$")>;
|
|
|
710 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "SQXBR$")>;
|
|
|
711
|
|
|
712 // Load FP integer
|
|
|
713 def : InstRW<[FPU], (instregex "FIEBR(A)?$")>;
|
|
|
714 def : InstRW<[FPU], (instregex "FIDBR(A)?$")>;
|
|
|
715 def : InstRW<[FPU2, FPU2, Lat15, GroupAlone], (instregex "FIXBR(A)?$")>;
|
|
|
716
|
|
|
717 //===----------------------------------------------------------------------===//
|
|
|
718 // FP: Binary arithmetic
|
|
|
719 //===----------------------------------------------------------------------===//
|
|
|
720
|
|
|
721 // Addition
|
|
|
722 def : InstRW<[FPU, LSU, Lat12], (instregex "A(E|D)B$")>;
|
|
|
723 def : InstRW<[FPU], (instregex "A(E|D)BR$")>;
|
|
|
724 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "AXBR$")>;
|
|
|
725
|
|
|
726 // Subtraction
|
|
|
727 def : InstRW<[FPU, LSU, Lat12], (instregex "S(E|D)B$")>;
|
|
|
728 def : InstRW<[FPU], (instregex "S(E|D)BR$")>;
|
|
|
729 def : InstRW<[FPU2, FPU2, Lat20, GroupAlone], (instregex "SXBR$")>;
|
|
|
730
|
|
|
731 // Multiply
|
|
|
732 def : InstRW<[FPU, LSU, Lat12], (instregex "M(D|DE|EE)B$")>;
|
|
|
733 def : InstRW<[FPU], (instregex "M(D|DE|EE)BR$")>;
|
|
|
734 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "MXDB$")>;
|
|
|
735 def : InstRW<[FPU2, FPU2, Lat10, GroupAlone], (instregex "MXDBR$")>;
|
|
|
736 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "MXBR$")>;
|
|
|
737
|
|
|
738 // Multiply and add / subtract
|
|
|
739 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>;
|
|
|
740 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
|
|
|
741 def : InstRW<[FPU, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>;
|
|
|
742 def : InstRW<[FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
|
|
|
743
|
|
|
744 // Division
|
|
|
745 def : InstRW<[FPU, LSU, Lat30], (instregex "D(E|D)B$")>;
|
|
|
746 def : InstRW<[FPU, Lat30], (instregex "D(E|D)BR$")>;
|
|
|
747 def : InstRW<[FPU2, FPU2, Lat30, GroupAlone], (instregex "DXBR$")>;
|
|
|
748
|
|
|
749 //===----------------------------------------------------------------------===//
|
|
|
750 // FP: Comparisons
|
|
|
751 //===----------------------------------------------------------------------===//
|
|
|
752
|
|
|
753 // Compare
|
|
|
754 def : InstRW<[FPU, LSU, Lat12], (instregex "C(E|D)B$")>;
|
|
|
755 def : InstRW<[FPU], (instregex "C(E|D)BR$")>;
|
|
|
756 def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
|
|
|
757
|
|
|
758 // Test Data Class
|
|
|
759 def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
|
|
|
760 def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
|
|
|
761
|
|
|
762 }
|
|
|
763
|
