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annotate test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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7d135dc70f03 LLVM 3.9
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1 ;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s
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2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s
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3
7d135dc70f03 LLVM 3.9
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4 ; CHECK-LABEL: {{^}}v1:
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1172e4bd9c6f update 4.0.0
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5 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd
1172e4bd9c6f update 4.0.0
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6 define amdgpu_ps void @v1(i32 %a1) {
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7 entry:
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8 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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9 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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10 %2 = extractelement <4 x float> %1, i32 0
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11 %3 = extractelement <4 x float> %1, i32 2
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12 %4 = extractelement <4 x float> %1, i32 3
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13 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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14 ret void
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15 }
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16
7d135dc70f03 LLVM 3.9
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17 ; CHECK-LABEL: {{^}}v2:
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1172e4bd9c6f update 4.0.0
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18 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb
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19 define amdgpu_ps void @v2(i32 %a1) {
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20 entry:
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21 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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22 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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23 %2 = extractelement <4 x float> %1, i32 0
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24 %3 = extractelement <4 x float> %1, i32 1
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25 %4 = extractelement <4 x float> %1, i32 3
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26 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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27 ret void
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28 }
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29
7d135dc70f03 LLVM 3.9
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30 ; CHECK-LABEL: {{^}}v3:
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1172e4bd9c6f update 4.0.0
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31 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe
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32 define amdgpu_ps void @v3(i32 %a1) {
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33 entry:
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34 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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35 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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36 %2 = extractelement <4 x float> %1, i32 1
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37 %3 = extractelement <4 x float> %1, i32 2
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38 %4 = extractelement <4 x float> %1, i32 3
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39 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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40 ret void
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41 }
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42
7d135dc70f03 LLVM 3.9
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43 ; CHECK-LABEL: {{^}}v4:
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44 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7
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45 define amdgpu_ps void @v4(i32 %a1) {
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46 entry:
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47 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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48 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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49 %2 = extractelement <4 x float> %1, i32 0
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50 %3 = extractelement <4 x float> %1, i32 1
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51 %4 = extractelement <4 x float> %1, i32 2
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52 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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53 ret void
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54 }
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55
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56 ; CHECK-LABEL: {{^}}v5:
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1172e4bd9c6f update 4.0.0
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57 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa
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58 define amdgpu_ps void @v5(i32 %a1) {
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59 entry:
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60 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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61 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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62 %2 = extractelement <4 x float> %1, i32 1
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63 %3 = extractelement <4 x float> %1, i32 3
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64 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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65 ret void
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66 }
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67
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68 ; CHECK-LABEL: {{^}}v6:
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1172e4bd9c6f update 4.0.0
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69 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6
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70 define amdgpu_ps void @v6(i32 %a1) {
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71 entry:
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72 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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73 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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74 %2 = extractelement <4 x float> %1, i32 1
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75 %3 = extractelement <4 x float> %1, i32 2
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76 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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77 ret void
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78 }
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79
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80 ; CHECK-LABEL: {{^}}v7:
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1172e4bd9c6f update 4.0.0
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81 ; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9
1172e4bd9c6f update 4.0.0
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82 define amdgpu_ps void @v7(i32 %a1) {
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83 entry:
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84 %0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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85 %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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86 %2 = extractelement <4 x float> %1, i32 0
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87 %3 = extractelement <4 x float> %1, i32 3
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88 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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89 ret void
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90 }
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91
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92 declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone
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93
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94 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)