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120
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1 ; Test load and zero rightmost byte.
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2 ;
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3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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4
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5 ; Check LZRF with no displacement.
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6 define i32 @f1(i32 *%src) {
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7 ; CHECK-LABEL: f1:
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8 ; CHECK: lzrf %r2, 0(%r2)
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9 ; CHECK: br %r14
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10 %val = load i32, i32 *%src
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11 %and = and i32 %val, 4294967040
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12 ret i32 %and
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13 }
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14
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15 ; Check the high end of the LZRF range.
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16 define i32 @f2(i32 *%src) {
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17 ; CHECK-LABEL: f2:
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18 ; CHECK: lzrf %r2, 524284(%r2)
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19 ; CHECK: br %r14
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20 %ptr = getelementptr i32, i32 *%src, i64 131071
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21 %val = load i32, i32 *%ptr
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22 %and = and i32 %val, 4294967040
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23 ret i32 %and
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24 }
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25
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26 ; Check the next word up, which needs separate address logic.
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27 ; Other sequences besides this one would be OK.
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28 define i32 @f3(i32 *%src) {
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29 ; CHECK-LABEL: f3:
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30 ; CHECK: agfi %r2, 524288
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31 ; CHECK: lzrf %r2, 0(%r2)
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32 ; CHECK: br %r14
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33 %ptr = getelementptr i32, i32 *%src, i64 131072
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34 %val = load i32, i32 *%ptr
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35 %and = and i32 %val, 4294967040
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36 ret i32 %and
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37 }
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38
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39 ; Check the high end of the negative LZRF range.
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40 define i32 @f4(i32 *%src) {
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41 ; CHECK-LABEL: f4:
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42 ; CHECK: lzrf %r2, -4(%r2)
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43 ; CHECK: br %r14
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44 %ptr = getelementptr i32, i32 *%src, i64 -1
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45 %val = load i32, i32 *%ptr
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46 %and = and i32 %val, 4294967040
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47 ret i32 %and
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48 }
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49
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50 ; Check the low end of the LZRF range.
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51 define i32 @f5(i32 *%src) {
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52 ; CHECK-LABEL: f5:
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53 ; CHECK: lzrf %r2, -524288(%r2)
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54 ; CHECK: br %r14
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55 %ptr = getelementptr i32, i32 *%src, i64 -131072
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56 %val = load i32, i32 *%ptr
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57 %and = and i32 %val, 4294967040
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58 ret i32 %and
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59 }
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60
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61 ; Check the next word down, which needs separate address logic.
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62 ; Other sequences besides this one would be OK.
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63 define i32 @f6(i32 *%src) {
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64 ; CHECK-LABEL: f6:
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65 ; CHECK: agfi %r2, -524292
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66 ; CHECK: lzrf %r2, 0(%r2)
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67 ; CHECK: br %r14
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68 %ptr = getelementptr i32, i32 *%src, i64 -131073
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69 %val = load i32, i32 *%ptr
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70 %and = and i32 %val, 4294967040
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71 ret i32 %and
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72 }
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73
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74 ; Check that LZRF allows an index.
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75 define i32 @f7(i64 %src, i64 %index) {
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76 ; CHECK-LABEL: f7:
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77 ; CHECK: lzrf %r2, 524287(%r3,%r2)
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78 ; CHECK: br %r14
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79 %add1 = add i64 %src, %index
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80 %add2 = add i64 %add1, 524287
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81 %ptr = inttoptr i64 %add2 to i32 *
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82 %val = load i32 , i32 *%ptr
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83 %and = and i32 %val, 4294967040
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84 ret i32 %and
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85 }
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86
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87 ; Check LZRG with no displacement.
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88 define i64 @f8(i64 *%src) {
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89 ; CHECK-LABEL: f8:
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90 ; CHECK: lzrg %r2, 0(%r2)
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91 ; CHECK: br %r14
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92 %val = load i64, i64 *%src
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93 %and = and i64 %val, 18446744073709551360
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94 ret i64 %and
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95 }
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96
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97 ; Check the high end of the LZRG range.
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98 define i64 @f9(i64 *%src) {
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99 ; CHECK-LABEL: f9:
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100 ; CHECK: lzrg %r2, 524280(%r2)
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101 ; CHECK: br %r14
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102 %ptr = getelementptr i64, i64 *%src, i64 65535
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103 %val = load i64, i64 *%ptr
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104 %and = and i64 %val, 18446744073709551360
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105 ret i64 %and
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106 }
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107
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108 ; Check the next word up, which needs separate address logic.
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109 ; Other sequences besides this one would be OK.
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110 define i64 @f10(i64 *%src) {
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111 ; CHECK-LABEL: f10:
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112 ; CHECK: agfi %r2, 524288
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113 ; CHECK: lzrg %r2, 0(%r2)
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114 ; CHECK: br %r14
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115 %ptr = getelementptr i64, i64 *%src, i64 65536
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116 %val = load i64, i64 *%ptr
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117 %and = and i64 %val, 18446744073709551360
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118 ret i64 %and
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119 }
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120
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121 ; Check the high end of the negative LZRG range.
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122 define i64 @f11(i64 *%src) {
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123 ; CHECK-LABEL: f11:
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124 ; CHECK: lzrg %r2, -8(%r2)
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125 ; CHECK: br %r14
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126 %ptr = getelementptr i64, i64 *%src, i64 -1
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127 %val = load i64, i64 *%ptr
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128 %and = and i64 %val, 18446744073709551360
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129 ret i64 %and
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130 }
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131
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132 ; Check the low end of the LZRG range.
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133 define i64 @f12(i64 *%src) {
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134 ; CHECK-LABEL: f12:
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135 ; CHECK: lzrg %r2, -524288(%r2)
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136 ; CHECK: br %r14
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137 %ptr = getelementptr i64, i64 *%src, i64 -65536
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138 %val = load i64, i64 *%ptr
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139 %and = and i64 %val, 18446744073709551360
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140 ret i64 %and
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141 }
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142
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143 ; Check the next word down, which needs separate address logic.
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144 ; Other sequences besides this one would be OK.
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145 define i64 @f13(i64 *%src) {
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146 ; CHECK-LABEL: f13:
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147 ; CHECK: agfi %r2, -524296
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148 ; CHECK: lzrg %r2, 0(%r2)
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149 ; CHECK: br %r14
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150 %ptr = getelementptr i64, i64 *%src, i64 -65537
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151 %val = load i64, i64 *%ptr
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152 %and = and i64 %val, 18446744073709551360
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153 ret i64 %and
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154 }
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155
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156 ; Check that LZRG allows an index.
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157 define i64 @f14(i64 %src, i64 %index) {
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158 ; CHECK-LABEL: f14:
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159 ; CHECK: lzrg %r2, 524287(%r3,%r2)
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160 ; CHECK: br %r14
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161 %add1 = add i64 %src, %index
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162 %add2 = add i64 %add1, 524287
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163 %ptr = inttoptr i64 %add2 to i64 *
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164 %val = load i64 , i64 *%ptr
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165 %and = and i64 %val, 18446744073709551360
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166 ret i64 %and
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167 }
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168
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169 ; Check LLZRGF with no displacement.
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170 define i64 @f15(i32 *%src) {
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171 ; CHECK-LABEL: f15:
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172 ; CHECK: llzrgf %r2, 0(%r2)
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173 ; CHECK: br %r14
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174 %val = load i32, i32 *%src
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175 %ext = zext i32 %val to i64
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176 %and = and i64 %ext, 18446744073709551360
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177 ret i64 %and
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178 }
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179
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180 ; ... and the other way around.
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181 define i64 @f16(i32 *%src) {
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182 ; CHECK-LABEL: f16:
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183 ; CHECK: llzrgf %r2, 0(%r2)
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184 ; CHECK: br %r14
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185 %val = load i32, i32 *%src
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186 %and = and i32 %val, 4294967040
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187 %ext = zext i32 %and to i64
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188 ret i64 %ext
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189 }
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190
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191 ; Check the high end of the LLZRGF range.
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192 define i64 @f17(i32 *%src) {
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193 ; CHECK-LABEL: f17:
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194 ; CHECK: llzrgf %r2, 524284(%r2)
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195 ; CHECK: br %r14
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196 %ptr = getelementptr i32, i32 *%src, i64 131071
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197 %val = load i32, i32 *%ptr
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198 %and = and i32 %val, 4294967040
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199 %ext = zext i32 %and to i64
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200 ret i64 %ext
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201 }
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202
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203 ; Check the next word up, which needs separate address logic.
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204 ; Other sequences besides this one would be OK.
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205 define i64 @f18(i32 *%src) {
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206 ; CHECK-LABEL: f18:
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207 ; CHECK: agfi %r2, 524288
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208 ; CHECK: llzrgf %r2, 0(%r2)
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209 ; CHECK: br %r14
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210 %ptr = getelementptr i32, i32 *%src, i64 131072
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211 %val = load i32, i32 *%ptr
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212 %and = and i32 %val, 4294967040
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213 %ext = zext i32 %and to i64
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214 ret i64 %ext
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215 }
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216
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217 ; Check the high end of the negative LLZRGF range.
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218 define i64 @f19(i32 *%src) {
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219 ; CHECK-LABEL: f19:
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220 ; CHECK: llzrgf %r2, -4(%r2)
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221 ; CHECK: br %r14
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222 %ptr = getelementptr i32, i32 *%src, i64 -1
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223 %val = load i32, i32 *%ptr
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224 %and = and i32 %val, 4294967040
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225 %ext = zext i32 %and to i64
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226 ret i64 %ext
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227 }
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228
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229 ; Check the low end of the LLZRGF range.
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230 define i64 @f20(i32 *%src) {
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231 ; CHECK-LABEL: f20:
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232 ; CHECK: llzrgf %r2, -524288(%r2)
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233 ; CHECK: br %r14
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234 %ptr = getelementptr i32, i32 *%src, i64 -131072
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235 %val = load i32, i32 *%ptr
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236 %and = and i32 %val, 4294967040
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237 %ext = zext i32 %and to i64
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238 ret i64 %ext
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239 }
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240
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241 ; Check the next word down, which needs separate address logic.
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242 ; Other sequences besides this one would be OK.
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243 define i64 @f21(i32 *%src) {
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244 ; CHECK-LABEL: f21:
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245 ; CHECK: agfi %r2, -524292
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246 ; CHECK: llzrgf %r2, 0(%r2)
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247 ; CHECK: br %r14
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248 %ptr = getelementptr i32, i32 *%src, i64 -131073
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249 %val = load i32, i32 *%ptr
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250 %and = and i32 %val, 4294967040
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251 %ext = zext i32 %and to i64
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252 ret i64 %ext
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253 }
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254
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255 ; Check that LLZRGF allows an index.
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256 define i64 @f22(i64 %src, i64 %index) {
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257 ; CHECK-LABEL: f22:
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258 ; CHECK: llzrgf %r2, 524287(%r3,%r2)
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259 ; CHECK: br %r14
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260 %add1 = add i64 %src, %index
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261 %add2 = add i64 %add1, 524287
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262 %ptr = inttoptr i64 %add2 to i32 *
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263 %val = load i32 , i32 *%ptr
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264 %and = and i32 %val, 4294967040
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265 %ext = zext i32 %and to i64
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266 ret i64 %ext
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267 }
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268
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269 ; Check that we still get a RISBGN if the source is in a register.
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270 define i64 @f23(i32 %src) {
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271 ; CHECK-LABEL: f23:
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272 ; CHECK: risbgn %r2, %r2, 32, 183, 0
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273 ; CHECK: br %r14
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274 %and = and i32 %src, 4294967040
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275 %ext = zext i32 %and to i64
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276 ret i64 %ext
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277 }
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278
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