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annotate test/CodeGen/X86/merge-store-partially-alias-loads.ll @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents afa8332a0e37
children 803732b1fca8
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1 ; REQUIRES: asserts
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2 ; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
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3 ; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
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4
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5 ; It's OK to merge the load / store of the first 2 components, but
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6 ; they must not be placed on the same chain after merging.
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8 ; X86-LABEL: {{^}}merge_store_partial_overlap_load:
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9 ; X86-DAG: movzwl ([[BASEREG:%[a-z]+]]), %e[[LO2:[a-z]+]]
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10 ; X86-DAG: movb 2([[BASEREG]]), [[HI1:%[a-z]+]]
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11
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12 ; X86-NEXT: movw %[[LO2]], 1([[BASEREG]])
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13 ; X86-NEXT: movb [[HI1]], 3([[BASEREG]])
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14 ; X86-NEXT: retq
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16 ; DBGDAG-LABEL: Optimized lowered selection DAG: BB#0 'merge_store_partial_overlap_load:'
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17 ; DBGDAG: [[ENTRYTOKEN:t[0-9]+]]: ch = EntryToken
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18 ; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
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19 ; DBGDAG-DAG: [[ADDPTR:t[0-9]+]]: i64 = add [[BASEPTR]], Constant:i64<2>
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20
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21 ; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<LD2[%tmp81](align=1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i64
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22 ; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<LD1[%tmp12]> [[ENTRYTOKEN]], [[ADDPTR]], undef:i64
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24 ; DBGDAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1
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26 ; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<ST2[%tmp10](align=1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i64
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27 ; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<ST1[%tmp14]> [[ST2]], [[LD1]], t{{[0-9]+}}, undef:i64
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28 ; DBGDAG: X86ISD::RET_FLAG [[ST1]],
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29
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30 ; DBGDAG: Type-legalized selection DAG: BB#0 'merge_store_partial_overlap_load:'
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31 define void @merge_store_partial_overlap_load([4 x i8]* %tmp) {
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32 %tmp8 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 0
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33 %tmp10 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 1
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34 %tmp12 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 2
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35 %tmp14 = getelementptr [4 x i8], [4 x i8]* %tmp, i32 0, i8 3
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37 %tmp9 = load i8, i8* %tmp8, align 1 ; base + 0
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38 %tmp11 = load i8, i8* %tmp10, align 1 ; base + 1
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39 %tmp13 = load i8, i8* %tmp12, align 1 ; base + 2
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40
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41 store i8 %tmp9, i8* %tmp10, align 1 ; base + 1
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42 store i8 %tmp11, i8* %tmp12, align 1 ; base + 2
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43 store i8 %tmp13, i8* %tmp14, align 1 ; base + 3
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44
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45 ; Should emit
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46 ; load base + 0, base + 1
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47 ; store base + 1, base + 2
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48 ; load base + 2
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49 ; store base + 3
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50
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51 ret void
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52 }