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150
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1 ..
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2 **************************************************
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3 * *
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4 * Automatically generated file, do not edit! *
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5 * *
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6 **************************************************
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7
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8 .. _amdgpu_synid9_hwreg:
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9
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10 hwreg
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11 ===========================
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12
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13 Bits of a hardware register being accessed.
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14
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15 The bits of this operand have the following meaning:
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16
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17 ======= ===================== ============
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18 Bits Description Value Range
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19 ======= ===================== ============
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20 5:0 Register *id*. 0..63
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21 10:6 First bit *offset*. 0..31
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22 15:11 *Size* in bits. 1..32
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23 ======= ===================== ============
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24
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25 This operand may be specified as one of the following:
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26
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27 * An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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28 * An *hwreg* value described below.
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29
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30 ==================================== ============================================================================
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31 Hwreg Value Syntax Description
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32 ==================================== ============================================================================
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33 hwreg({0..63}) All bits of a register indicated by its *id*.
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34 hwreg(<*name*>) All bits of a register indicated by its *name*.
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35 hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
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36 hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
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37 ==================================== ============================================================================
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38
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39 Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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40 or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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41
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42 Defined register *names* include:
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43
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44 =================== ==========================================
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45 Name Description
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46 =================== ==========================================
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47 HW_REG_MODE Shader writeable mode bits.
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48 HW_REG_STATUS Shader read-only status.
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49 HW_REG_TRAPSTS Trap status.
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50 HW_REG_HW_ID Id of wave, simd, compute unit, etc.
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51 HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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52 HW_REG_LDS_ALLOC Per-wave LDS allocation.
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53 HW_REG_IB_STS Counters of outstanding instructions.
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54 HW_REG_SH_MEM_BASES Memory aperture.
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55 =================== ==========================================
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56
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57 Examples:
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58
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59 .. parsed-literal::
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60
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61 reg = 1
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62 offset = 2
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63 size = 4
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64 hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
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65
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66 s_getreg_b32 s2, 0x1881
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67 s_getreg_b32 s2, hwreg_enc // the same as above
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68 s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
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69 s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
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70
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71 s_getreg_b32 s2, hwreg(15)
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72 s_getreg_b32 s2, hwreg(51, 1, 31)
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73 s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
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74
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