annotate llvm/lib/Target/Hexagon/HexagonIICScalar.td @ 150:1d019706d866

LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 0572611fdcc8
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1 //===--- HexagonIICScalar.td ----------------------------------------------===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8
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9 // These itinerary class descriptions are based on the instruction timing
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10 // classes as per V62. Curretnly, they are just extracted from
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11 // HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
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12
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13 class PseudoItin {
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14 list<InstrItinData> PseudoItin_list = [
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15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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16 [1, 1, 1]>,
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17 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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18 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
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19 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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20 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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21 ];
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22 }
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23
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24 class ScalarItin {
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25 list<InstrItinData> ScalarItin_list = [
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26 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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27 [3, 1], [Hex_FWD, Hex_FWD]>,
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28 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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29 [1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
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30 ];
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31 }