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1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
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2 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s
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3 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
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4
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5 ; DAGCombiner will transform:
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6 ; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))
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7 ; unless isFabsFree returns true
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8
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9 ; GCN-LABEL: {{^}}s_fabs_free_f16:
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10 ; GCN: s_load_dword [[VAL:s[0-9]+]]
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11 ; GCN: s_and_b32 [[RESULT:s[0-9]+]], [[VAL]], 0x7fff
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12 ; GCN: v_mov_b32_e32 [[V_RESULT:v[0-9]+]], [[RESULT]]
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13 ; GCN: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[V_RESULT]]
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14 define amdgpu_kernel void @s_fabs_free_f16(half addrspace(1)* %out, i16 %in) {
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15 %bc= bitcast i16 %in to half
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16 %fabs = call half @llvm.fabs.f16(half %bc)
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17 store half %fabs, half addrspace(1)* %out
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18 ret void
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19 }
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20
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21 ; GCN-LABEL: {{^}}s_fabs_f16:
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22 ; GCN: s_load_dword [[VAL:s[0-9]+]]
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23 ; GCN: s_and_b32 [[RESULT:s[0-9]+]], [[VAL]], 0x7fff
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24 ; GCN: v_mov_b32_e32 [[V_RESULT:v[0-9]+]], [[RESULT]]
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25 ; GCN: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[V_RESULT]]
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26 define amdgpu_kernel void @s_fabs_f16(half addrspace(1)* %out, half %in) {
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27 %fabs = call half @llvm.fabs.f16(half %in)
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28 store half %fabs, half addrspace(1)* %out
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29 ret void
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30 }
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31
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32 ; GCN-LABEL: {{^}}s_fabs_v2f16:
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33 ; GCN: s_load_dword [[VAL:s[0-9]+]]
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34 ; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0x7fff7fff
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35 define amdgpu_kernel void @s_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) {
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36 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
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37 store <2 x half> %fabs, <2 x half> addrspace(1)* %out
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38 ret void
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39 }
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40
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41 ; GCN-LABEL: {{^}}s_fabs_v4f16:
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42 ; CI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2
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43 ; GFX89: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8
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44
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45 ; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x7fff7fff
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46 ; GCN-DAG: s_and_b32 s{{[0-9]+}}, s[[LO]], [[MASK]]
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47 ; GCN-DAG: s_and_b32 s{{[0-9]+}}, s[[HI]], [[MASK]]
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48 ; GCN: {{flat|global}}_store_dwordx2
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49 define amdgpu_kernel void @s_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) {
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50 %fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in)
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51 store <4 x half> %fabs, <4 x half> addrspace(1)* %out
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52 ret void
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53 }
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54
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55 ; GCN-LABEL: {{^}}fabs_fold_f16:
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56 ; GCN: s_load_dword [[IN0:s[0-9]+]]
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57 ; GCN-DAG: s_lshr_b32 [[IN1:s[0-9]+]], [[IN0]], 16
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58
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59 ; CI-DAG: v_cvt_f32_f16_e64 [[CVT0:v[0-9]+]], |[[IN0]]|
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60 ; CI-DAG: v_cvt_f32_f16_e32 [[ABS_CVT1:v[0-9]+]], [[IN1]]
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61 ; CI-DAG: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[CVT0]], [[ABS_CVT1]]
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62 ; CI-DAG: v_cvt_f16_f32_e32 [[CVTRESULT:v[0-9]+]], [[RESULT]]
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63 ; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[CVTRESULT]]
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64
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65 ; GFX89-NOT: and
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66 ; GFX89: v_mov_b32_e32 [[V_IN1:v[0-9]+]], [[IN1]]
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67 ; GFX89: v_mul_f16_e64 [[RESULT:v[0-9]+]], |[[IN0]]|, [[V_IN1]]
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68 ; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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69 define amdgpu_kernel void @fabs_fold_f16(half addrspace(1)* %out, half %in0, half %in1) {
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70 %fabs = call half @llvm.fabs.f16(half %in0)
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71 %fmul = fmul half %fabs, %in1
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72 store half %fmul, half addrspace(1)* %out
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73 ret void
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74 }
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75
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76 ; GCN-LABEL: {{^}}v_fabs_v2f16:
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77 ; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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78 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7fff7fff, [[VAL]]
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79 define amdgpu_kernel void @v_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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80 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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81 %gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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82 %gep.out = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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83 %val = load <2 x half>, <2 x half> addrspace(1)* %gep.in, align 2
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84 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)
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85 store <2 x half> %fabs, <2 x half> addrspace(1)* %gep.out
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86 ret void
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87 }
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88
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89 ; GCN-LABEL: {{^}}fabs_free_v2f16:
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90 ; GCN: s_load_dword [[VAL:s[0-9]+]]
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91 ; GCN: s_and_b32 s{{[0-9]+}}, [[VAL]], 0x7fff7fff
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92 define amdgpu_kernel void @fabs_free_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 {
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93 %bc = bitcast i32 %in to <2 x half>
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94 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %bc)
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95 store <2 x half> %fabs, <2 x half> addrspace(1)* %out
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96 ret void
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97 }
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98
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99 ; FIXME: Should do fabs after conversion to avoid converting multiple
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100 ; times in this particular case.
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101
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102 ; GCN-LABEL: {{^}}v_fabs_fold_self_v2f16:
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103 ; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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104
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105 ; CI: v_lshrrev_b32_e32 [[VREG:v[0-9]+]], 16, v{{[0-9]+}}
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106 ; CI: v_cvt_f32_f16_e32 [[NORM:v[0-9]+]], [[VREG]]
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107 ; CI: v_cvt_f32_f16_e64 [[ABS:v[0-9]+]], {{\|}}[[VREG]]{{\|}}
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108 ; CI: v_mul_f32_e32 v{{[0-9]+}}, [[ABS]], [[NORM]]
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109 ; CI: v_cvt_f16_f32
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110 ; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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111 ; CI: v_cvt_f16_f32
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112
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113 ; VI: v_mul_f16_sdwa v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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114 ; VI: v_mul_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}
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115
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116 ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]]
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117 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[FABS]], v{{[0-9]+$}}
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118 define amdgpu_kernel void @v_fabs_fold_self_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 {
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119 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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120 %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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121 %val = load <2 x half>, <2 x half> addrspace(1)* %gep
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122 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)
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123 %fmul = fmul <2 x half> %fabs, %val
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124 store <2 x half> %fmul, <2 x half> addrspace(1)* %out
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125 ret void
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126 }
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127
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128 ; GCN-LABEL: {{^}}v_fabs_fold_v2f16:
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129 ; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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130
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131 ; CI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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132 ; CI: v_cvt_f32_f16_e32
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133 ; CI: v_cvt_f32_f16_e32
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134 ; CI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}}
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135 ; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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136 ; CI: v_cvt_f16_f32
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137 ; CI: v_mul_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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138 ; CI: v_cvt_f16_f32
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139
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140 ; VI: v_mul_f16_sdwa v{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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141 ; VI: v_mul_f16_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, s{{[0-9]+}}
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142
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143 ; GFX9: v_and_b32_e32 [[FABS:v[0-9]+]], 0x7fff7fff, [[VAL]]
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144 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[FABS]], s{{[0-9]+$}}
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145 define amdgpu_kernel void @v_fabs_fold_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(1)* %in, i32 %other.val) #0 {
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146 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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147 %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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148 %val = load <2 x half>, <2 x half> addrspace(1)* %gep
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149 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)
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150 %other.val.cvt = bitcast i32 %other.val to <2 x half>
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151 %fmul = fmul <2 x half> %fabs, %other.val.cvt
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152 store <2 x half> %fmul, <2 x half> addrspace(1)* %out
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153 ret void
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154 }
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155
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156 ; GCN-LABEL: {{^}}v_extract_fabs_fold_v2f16:
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157 ; GCN-DAG: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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158 ; CI-DAG: v_mul_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}}
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159 ; CI-DAG: v_add_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}}
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160
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161 ; GFX89-DAG: v_mul_f16_e64 v{{[0-9]+}}, |[[VAL]]|, 4.0
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162 ; GFX89-DAG: v_mov_b32_e32 [[CONST2:v[0-9]+]], 0x4000
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163 ; GFX89-DAG: v_add_f16_sdwa v{{[0-9]+}}, |[[VAL]]|, [[CONST2]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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164 define amdgpu_kernel void @v_extract_fabs_fold_v2f16(<2 x half> addrspace(1)* %in) #0 {
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165 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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166 %gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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167 %val = load <2 x half>, <2 x half> addrspace(1)* %gep.in
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168 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)
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169 %elt0 = extractelement <2 x half> %fabs, i32 0
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170 %elt1 = extractelement <2 x half> %fabs, i32 1
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171
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172 %fmul0 = fmul half %elt0, 4.0
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173 %fadd1 = fadd half %elt1, 2.0
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174 store volatile half %fmul0, half addrspace(1)* undef
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175 store volatile half %fadd1, half addrspace(1)* undef
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176 ret void
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177 }
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178
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179 ; GCN-LABEL: {{^}}v_extract_fabs_no_fold_v2f16:
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180 ; GCN: {{flat|global}}_load_dword [[VAL:v[0-9]+]]
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181 ; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 0x7fff7fff, [[VAL]]
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182
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183
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184 ; VI: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, 16, 15
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185 ; VI: flat_store_short
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186
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187 ; GFX9: global_store_short_d16_hi v{{\[[0-9]+:[0-9]+\]}}, [[AND]], off
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188 define amdgpu_kernel void @v_extract_fabs_no_fold_v2f16(<2 x half> addrspace(1)* %in) #0 {
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189 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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190 %gep.in = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %in, i32 %tid
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191 %val = load <2 x half>, <2 x half> addrspace(1)* %gep.in
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192 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %val)
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193 %elt0 = extractelement <2 x half> %fabs, i32 0
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194 %elt1 = extractelement <2 x half> %fabs, i32 1
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195 store volatile half %elt0, half addrspace(1)* undef
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196 store volatile half %elt1, half addrspace(1)* undef
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197 ret void
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198 }
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199
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200 declare half @llvm.fabs.f16(half) #1
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201 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1
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202 declare <4 x half> @llvm.fabs.v4f16(<4 x half>) #1
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203 declare i32 @llvm.amdgcn.workitem.id.x() #1
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204
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205 attributes #0 = { nounwind }
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206 attributes #1 = { nounwind readnone }
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