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annotate llvm/test/CodeGen/AMDGPU/fp_to_sint.ll @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 2e18cbf3894f
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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN
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3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=EG --check-prefix=FUNC
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4
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5 declare float @llvm.fabs.f32(float) #1
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6
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7 ; FUNC-LABEL: {{^}}fp_to_sint_i32:
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8 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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9 ; SI: v_cvt_i32_f32_e32
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10 ; SI: s_endpgm
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11 define amdgpu_kernel void @fp_to_sint_i32(i32 addrspace(1)* %out, float %in) {
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12 %conv = fptosi float %in to i32
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13 store i32 %conv, i32 addrspace(1)* %out
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14 ret void
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15 }
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16
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17 ; FUNC-LABEL: {{^}}fp_to_sint_i32_fabs:
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18 ; SI: v_cvt_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
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19 define amdgpu_kernel void @fp_to_sint_i32_fabs(i32 addrspace(1)* %out, float %in) {
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20 %in.fabs = call float @llvm.fabs.f32(float %in)
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21 %conv = fptosi float %in.fabs to i32
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22 store i32 %conv, i32 addrspace(1)* %out
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23 ret void
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24 }
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25
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26 ; FUNC-LABEL: {{^}}fp_to_sint_v2i32:
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27 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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28 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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29 ; SI: v_cvt_i32_f32_e32
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30 ; SI: v_cvt_i32_f32_e32
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31 define amdgpu_kernel void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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32 %result = fptosi <2 x float> %in to <2 x i32>
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33 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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34 ret void
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35 }
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36
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37 ; FUNC-LABEL: {{^}}fp_to_sint_v4i32:
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38 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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39 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}}
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40 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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41 ; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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42 ; SI: v_cvt_i32_f32_e32
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43 ; SI: v_cvt_i32_f32_e32
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44 ; SI: v_cvt_i32_f32_e32
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45 ; SI: v_cvt_i32_f32_e32
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46 define amdgpu_kernel void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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47 %value = load <4 x float>, <4 x float> addrspace(1) * %in
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48 %result = fptosi <4 x float> %value to <4 x i32>
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49 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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50 ret void
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51 }
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52
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53 ; FUNC-LABEL: {{^}}fp_to_sint_i64:
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54
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55 ; EG-DAG: AND_INT
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56 ; EG-DAG: LSHR
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57 ; EG-DAG: SUB_INT
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58 ; EG-DAG: AND_INT
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59 ; EG-DAG: ASHR
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60 ; EG-DAG: AND_INT
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61 ; EG-DAG: OR_INT
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62 ; EG-DAG: SUB_INT
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63 ; EG-DAG: LSHL
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64 ; EG-DAG: LSHL
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65 ; EG-DAG: SUB_INT
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66 ; EG-DAG: LSHR
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67 ; EG-DAG: LSHR
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68 ; EG-DAG: SETGT_UINT
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69 ; EG-DAG: SETGT_INT
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70 ; EG-DAG: XOR_INT
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71 ; EG-DAG: XOR_INT
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72 ; EG: SUB_INT
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73 ; EG-DAG: SUB_INT
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74 ; EG-DAG: CNDE_INT
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75 ; EG-DAG: CNDE_INT
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76
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77 ; Check that the compiler doesn't crash with a "cannot select" error
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78 ; SI: s_endpgm
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79 define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
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80 entry:
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81 %0 = fptosi float %in to i64
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82 store i64 %0, i64 addrspace(1)* %out
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83 ret void
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84 }
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85
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86 ; FUNC: {{^}}fp_to_sint_v2i64:
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87 ; EG-DAG: AND_INT
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88 ; EG-DAG: LSHR
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89 ; EG-DAG: SUB_INT
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90 ; EG-DAG: AND_INT
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91 ; EG-DAG: ASHR
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92 ; EG-DAG: AND_INT
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93 ; EG-DAG: OR_INT
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94 ; EG-DAG: SUB_INT
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95 ; EG-DAG: LSHL
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96 ; EG-DAG: LSHL
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97 ; EG-DAG: SUB_INT
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98 ; EG-DAG: LSHR
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99 ; EG-DAG: LSHR
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100 ; EG-DAG: SETGT_UINT
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101 ; EG-DAG: SETGT_INT
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102 ; EG-DAG: XOR_INT
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103 ; EG-DAG: XOR_INT
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104 ; EG-DAG: SUB_INT
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105 ; EG-DAG: SUB_INT
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106 ; EG-DAG: CNDE_INT
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107 ; EG-DAG: CNDE_INT
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108 ; EG-DAG: AND_INT
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109 ; EG-DAG: LSHR
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110 ; EG-DAG: SUB_INT
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111 ; EG-DAG: AND_INT
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112 ; EG-DAG: ASHR
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113 ; EG-DAG: AND_INT
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114 ; EG-DAG: OR_INT
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115 ; EG-DAG: SUB_INT
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116 ; EG-DAG: LSHL
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117 ; EG-DAG: LSHL
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118 ; EG-DAG: SUB_INT
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119 ; EG-DAG: LSHR
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120 ; EG-DAG: LSHR
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121 ; EG-DAG: SETGT_UINT
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122 ; EG-DAG: SETGT_INT
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123 ; EG-DAG: XOR_INT
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124 ; EG-DAG: XOR_INT
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125 ; EG-DAG: SUB_INT
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126 ; EG-DAG: SUB_INT
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127 ; EG-DAG: CNDE_INT
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128 ; EG-DAG: CNDE_INT
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129
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130 ; SI: s_endpgm
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131 define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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132 %conv = fptosi <2 x float> %x to <2 x i64>
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133 store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
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134 ret void
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135 }
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136
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137 ; FUNC: {{^}}fp_to_sint_v4i64:
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138 ; EG-DAG: AND_INT
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139 ; EG-DAG: LSHR
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140 ; EG-DAG: SUB_INT
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141 ; EG-DAG: AND_INT
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142 ; EG-DAG: ASHR
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143 ; EG-DAG: AND_INT
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144 ; EG-DAG: OR_INT
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145 ; EG-DAG: SUB_INT
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146 ; EG-DAG: LSHL
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147 ; EG-DAG: LSHL
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148 ; EG-DAG: SUB_INT
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149 ; EG-DAG: LSHR
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150 ; EG-DAG: LSHR
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151 ; EG-DAG: SETGT_UINT
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152 ; EG-DAG: SETGT_INT
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153 ; EG-DAG: XOR_INT
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154 ; EG-DAG: XOR_INT
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155 ; EG-DAG: SUB_INT
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156 ; EG-DAG: SUB_INT
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157 ; EG-DAG: CNDE_INT
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158 ; EG-DAG: CNDE_INT
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159 ; EG-DAG: AND_INT
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160 ; EG-DAG: LSHR
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161 ; EG-DAG: SUB_INT
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162 ; EG-DAG: AND_INT
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163 ; EG-DAG: ASHR
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164 ; EG-DAG: AND_INT
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165 ; EG-DAG: OR_INT
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166 ; EG-DAG: SUB_INT
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167 ; EG-DAG: LSHL
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168 ; EG-DAG: LSHL
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169 ; EG-DAG: SUB_INT
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170 ; EG-DAG: LSHR
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171 ; EG-DAG: LSHR
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172 ; EG-DAG: SETGT_UINT
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173 ; EG-DAG: SETGT_INT
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174 ; EG-DAG: XOR_INT
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175 ; EG-DAG: XOR_INT
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176 ; EG-DAG: SUB_INT
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177 ; EG-DAG: SUB_INT
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178 ; EG-DAG: CNDE_INT
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179 ; EG-DAG: CNDE_INT
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180 ; EG-DAG: AND_INT
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181 ; EG-DAG: LSHR
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182 ; EG-DAG: SUB_INT
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183 ; EG-DAG: AND_INT
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184 ; EG-DAG: ASHR
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185 ; EG-DAG: AND_INT
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186 ; EG-DAG: OR_INT
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187 ; EG-DAG: SUB_INT
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188 ; EG-DAG: LSHL
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189 ; EG-DAG: LSHL
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190 ; EG-DAG: SUB_INT
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191 ; EG-DAG: LSHR
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192 ; EG-DAG: LSHR
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193 ; EG-DAG: SETGT_UINT
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194 ; EG-DAG: SETGT_INT
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195 ; EG-DAG: XOR_INT
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196 ; EG-DAG: XOR_INT
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197 ; EG-DAG: SUB_INT
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198 ; EG-DAG: SUB_INT
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199 ; EG-DAG: CNDE_INT
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200 ; EG-DAG: CNDE_INT
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201 ; EG-DAG: AND_INT
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202 ; EG-DAG: LSHR
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203 ; EG-DAG: SUB_INT
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204 ; EG-DAG: AND_INT
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205 ; EG-DAG: ASHR
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206 ; EG-DAG: AND_INT
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207 ; EG-DAG: OR_INT
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208 ; EG-DAG: SUB_INT
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209 ; EG-DAG: LSHL
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210 ; EG-DAG: LSHL
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211 ; EG-DAG: SUB_INT
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212 ; EG-DAG: LSHR
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213 ; EG-DAG: LSHR
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214 ; EG-DAG: SETGT_UINT
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215 ; EG-DAG: SETGT_INT
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216 ; EG-DAG: XOR_INT
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217 ; EG-DAG: XOR_INT
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218 ; EG-DAG: SUB_INT
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219 ; EG-DAG: SUB_INT
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220 ; EG-DAG: CNDE_INT
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221 ; EG-DAG: CNDE_INT
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222
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223 ; SI: s_endpgm
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224 define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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225 %conv = fptosi <4 x float> %x to <4 x i64>
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226 store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
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227 ret void
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228 }
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229
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230 ; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i1:
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231 ; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}}
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232
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233 ; EG: AND_INT
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234 ; EG: SETE_DX10 {{[*]?}} T{{[0-9]+}}.{{[XYZW]}}, KC0[2].Z, literal.y,
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235 ; EG-NEXT: -1082130432(-1.000000e+00)
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236 define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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237 %conv = fptosi float %in to i1
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238 store i1 %conv, i1 addrspace(1)* %out
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239 ret void
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240 }
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241
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242 ; FUNC-LABEL: {{^}}fp_to_uint_fabs_f32_to_i1:
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243 ; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, |s{{[0-9]+}}|
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244 define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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245 %in.fabs = call float @llvm.fabs.f32(float %in)
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246 %conv = fptosi float %in.fabs to i1
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247 store i1 %conv, i1 addrspace(1)* %out
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248 ret void
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249 }
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250
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251 ; FUNC-LABEL: {{^}}fp_to_sint_f32_i16:
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252 ; GCN: v_cvt_i32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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253 ; GCN: buffer_store_short [[VAL]]
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254 define amdgpu_kernel void @fp_to_sint_f32_i16(i16 addrspace(1)* %out, float %in) #0 {
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255 %sint = fptosi float %in to i16
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256 store i16 %sint, i16 addrspace(1)* %out
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257 ret void
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258 }
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259
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260 attributes #0 = { nounwind }
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261 attributes #1 = { nounwind readnone }