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150
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MOVREL,PREGFX9 %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MOVREL,PREGFX9 %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-vgpr-index-mode -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,IDXMODE,PREGFX9 %s
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4
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5 ; Tests for indirect addressing on SI, which is implemented using dynamic
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6 ; indexing of vectors.
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7
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8 ; Subtest below moved from file test/CodeGen/AMDGPU/indirect-addressing-si.ll
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9 ; to avoid gfx9 scheduling induced issues.
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10
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11
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12 ; GCN-LABEL: {{^}}insert_vgpr_offset_multiple_in_block:
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13 ; GCN-DAG: s_load_dwordx16 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT15:[0-9]+]]{{\]}}
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14 ; GCN-DAG: {{buffer|flat|global}}_load_dword [[IDX0:v[0-9]+]]
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15 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
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16
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17 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT15:[0-9]+]], s[[S_ELT15]]
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18 ; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
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19
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20 ; GCN-DAG: v_add_{{i32|u32}}_e32 [[IDX1:v[0-9]+]], vcc, 1, [[IDX0]]
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21
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22 ; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:
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23 ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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24 ; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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25 ; GCN: s_and_saveexec_b64 vcc, vcc
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26
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27 ; MOVREL: s_mov_b32 m0, [[READLANE]]
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28 ; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]]
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29
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30 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST)
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31 ; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]]
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32 ; IDXMODE: s_set_gpr_idx_off
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33
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34 ; GCN-NEXT: s_xor_b64 exec, exec, vcc
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35 ; GCN: s_cbranch_execnz [[LOOP0]]
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36
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37 ; FIXME: Redundant copy
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38 ; GCN: s_mov_b64 exec, [[MASK:s\[[0-9]+:[0-9]+\]]]
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39
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40 ; GCN: s_mov_b64 [[MASK]], exec
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41
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42 ; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
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43 ; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX1]]
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44 ; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX1]]
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45 ; GCN: s_and_saveexec_b64 vcc, vcc
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46
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47 ; MOVREL: s_mov_b32 m0, [[READLANE]]
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48 ; MOVREL-NEXT: v_movreld_b32_e32 v{{[0-9]+}}, 63
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49
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50 ; IDXMODE: s_set_gpr_idx_on [[READLANE]], gpr_idx(DST)
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51 ; IDXMODE-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 63
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52 ; IDXMODE: s_set_gpr_idx_off
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53
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54 ; GCN-NEXT: s_xor_b64 exec, exec, vcc
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55 ; GCN: s_cbranch_execnz [[LOOP1]]
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56
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57 ; GCN: buffer_store_dwordx4 v{{\[}}[[VEC_ELT0]]:
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58
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59 ; GCN: buffer_store_dword [[INS0]]
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60 define amdgpu_kernel void @insert_vgpr_offset_multiple_in_block(<16 x i32> addrspace(1)* %out0, <16 x i32> addrspace(1)* %out1, i32 addrspace(1)* %in, <16 x i32> %vec0) #0 {
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61 entry:
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62 %id = call i32 @llvm.amdgcn.workitem.id.x() #1
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63 %id.ext = zext i32 %id to i64
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64 %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %id.ext
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65 %idx0 = load volatile i32, i32 addrspace(1)* %gep
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66 %idx1 = add i32 %idx0, 1
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67 %live.out.val = call i32 asm sideeffect "v_mov_b32 $0, 62", "=v"()
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68 %vec1 = insertelement <16 x i32> %vec0, i32 %live.out.val, i32 %idx0
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69 %vec2 = insertelement <16 x i32> %vec1, i32 63, i32 %idx1
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70 store volatile <16 x i32> %vec2, <16 x i32> addrspace(1)* %out0
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71 %cmp = icmp eq i32 %id, 0
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72 br i1 %cmp, label %bb1, label %bb2
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73
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74 bb1:
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75 store volatile i32 %live.out.val, i32 addrspace(1)* undef
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76 br label %bb2
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77
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78 bb2:
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79 ret void
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80 }
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81
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82 declare i32 @llvm.amdgcn.workitem.id.x() #1
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83 declare void @llvm.amdgcn.s.barrier() #2
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84
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85 attributes #0 = { nounwind }
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86 attributes #1 = { nounwind readnone }
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87 attributes #2 = { nounwind convergent }
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