annotate llvm/test/CodeGen/AMDGPU/inlineasm-packed.ll @ 150:1d019706d866

LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 2e18cbf3894f
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rev   line source
150
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1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
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2
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3 ; GCN-LABEL: {{^}}inline_asm_input_v2i16:
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4 ; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}
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5 define amdgpu_kernel void @inline_asm_input_v2i16(i32 addrspace(1)* %out, <2 x i16> %in) #0 {
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6 entry:
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7 %val = call i32 asm "s_mov_b32 $0, $1", "=r,r"(<2 x i16> %in) #0
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8 store i32 %val, i32 addrspace(1)* %out
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9 ret void
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10 }
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11
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12 ; GCN-LABEL: {{^}}inline_asm_input_v2f16:
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13 ; GCN: s_mov_b32 s0, s{{[0-9]+}}
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14 define amdgpu_kernel void @inline_asm_input_v2f16(i32 addrspace(1)* %out, <2 x half> %in) #0 {
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15 entry:
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16 %val = call i32 asm "s_mov_b32 $0, $1", "=r,r"(<2 x half> %in) #0
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17 store i32 %val, i32 addrspace(1)* %out
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18 ret void
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19 }
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20
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21 ; GCN-LABEL: {{^}}inline_asm_output_v2i16:
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22 ; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}
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23 define amdgpu_kernel void @inline_asm_output_v2i16(<2 x i16> addrspace(1)* %out, i32 %in) #0 {
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24 entry:
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25 %val = call <2 x i16> asm "s_mov_b32 $0, $1", "=r,r"(i32 %in) #0
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26 store <2 x i16> %val, <2 x i16> addrspace(1)* %out
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27 ret void
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28 }
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29
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30 ; GCN-LABEL: {{^}}inline_asm_output_v2f16:
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31 ; GCN: v_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
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32 define amdgpu_kernel void @inline_asm_output_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 {
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33 entry:
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34 %val = call <2 x half> asm "v_mov_b32 $0, $1", "=v,r"(i32 %in) #0
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35 store <2 x half> %val, <2 x half> addrspace(1)* %out
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36 ret void
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37 }
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38
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39 ; GCN-LABEL: {{^}}inline_asm_packed_v2i16:
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40 ; GCN: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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41 define amdgpu_kernel void @inline_asm_packed_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %in0, <2 x i16> %in1) #0 {
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42 entry:
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43 %val = call <2 x i16> asm "v_pk_add_u16 $0, $1, $2", "=v,r,v"(<2 x i16> %in0, <2 x i16> %in1) #0
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44 store <2 x i16> %val, <2 x i16> addrspace(1)* %out
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45 ret void
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46 }
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47
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48 ; GCN-LABEL: {{^}}inline_asm_packed_v2f16:
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49 ; GCN: v_pk_add_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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50 define amdgpu_kernel void @inline_asm_packed_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in0, <2 x half> %in1) #0 {
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51 entry:
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52 %val = call <2 x half> asm "v_pk_add_f16 $0, $1, $2", "=v,r,v"(<2 x half> %in0, <2 x half> %in1) #0
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53 store <2 x half> %val, <2 x half> addrspace(1)* %out
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54 ret void
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55 }
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56
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57 attributes #0 = { nounwind }