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annotate llvm/test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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children 1f2b6ac9f198
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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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3
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4 declare i64 @llvm.amdgcn.qsad.pk.u16.u8(i64, i32, i64) #0
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5
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6 ; GCN-LABEL: {{^}}v_qsad_pk_u16_u8:
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7 ; GCN: v_qsad_pk_u16_u8 v[0:1], v[4:5], s{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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8 ; GCN-DAG: v_mov_b32_e32 v5, v1
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9 ; GCN-DAG: v_mov_b32_e32 v4, v0
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10 define amdgpu_kernel void @v_qsad_pk_u16_u8(i64 addrspace(1)* %out, i64 %src) {
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11 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[4:5]},v"(i64 %src) #0
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12 %tmp1 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 100, i64 100) #0
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13 %tmp2 = call i64 asm ";; force constraint", "=v,{v[4:5]}"(i64 %tmp1) #0
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14 store i64 %tmp2, i64 addrspace(1)* %out, align 4
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15 ret void
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16 }
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17
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18 ; GCN-LABEL: {{^}}v_qsad_pk_u16_u8_non_immediate:
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19 ; GCN: v_qsad_pk_u16_u8 v[0:1], v[2:3], v4, v[6:7]
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20 ; GCN-DAG: v_mov_b32_e32 v3, v1
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21 ; GCN-DAG: v_mov_b32_e32 v2, v0
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22 define amdgpu_kernel void @v_qsad_pk_u16_u8_non_immediate(i64 addrspace(1)* %out, i64 %src, i32 %a, i64 %b) {
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23 %tmp = call i64 asm "v_lsrlrev_b64 $0, $1, 1", "={v[2:3]},v"(i64 %src) #0
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24 %tmp1 = call i32 asm "v_mov_b32 $0, $1", "={v4},v"(i32 %a) #0
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25 %tmp2 = call i64 asm "v_lshlrev_b64 $0, $1, 1", "={v[6:7]},v"(i64 %b) #0
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26 %tmp3 = call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %tmp, i32 %tmp1, i64 %tmp2) #0
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27 %tmp4 = call i64 asm ";; force constraint", "=v,{v[2:3]}"(i64 %tmp3) #0
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28 store i64 %tmp4, i64 addrspace(1)* %out, align 4
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29 ret void
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30 }
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31
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32 attributes #0 = { nounwind readnone }