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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,VARIANT0 %s
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3 ; RUN: llc -march=amdgcn -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,VARIANT1 %s
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4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,VARIANT2 %s
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5 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,VARIANT3 %s
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6
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7 define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out, i32 %size) #0 {
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8 ; VARIANT0-LABEL: test_barrier:
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9 ; VARIANT0: ; %bb.0: ; %entry
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10 ; VARIANT0-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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11 ; VARIANT0-NEXT: s_load_dword s2, s[0:1], 0xb
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12 ; VARIANT0-NEXT: v_not_b32_e32 v3, v0
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13 ; VARIANT0-NEXT: s_mov_b32 s7, 0xf000
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14 ; VARIANT0-NEXT: s_mov_b32 s6, 0
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15 ; VARIANT0-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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16 ; VARIANT0-NEXT: v_mov_b32_e32 v2, 0
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17 ; VARIANT0-NEXT: s_waitcnt lgkmcnt(0)
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18 ; VARIANT0-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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19 ; VARIANT0-NEXT: s_waitcnt vmcnt(0) expcnt(0)
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20 ; VARIANT0-NEXT: s_barrier
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21 ; VARIANT0-NEXT: v_add_i32_e32 v3, vcc, s2, v3
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22 ; VARIANT0-NEXT: v_ashrrev_i32_e32 v4, 31, v3
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23 ; VARIANT0-NEXT: v_lshl_b64 v[3:4], v[3:4], 2
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24 ; VARIANT0-NEXT: buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
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25 ; VARIANT0-NEXT: s_waitcnt vmcnt(0)
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26 ; VARIANT0-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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27 ; VARIANT0-NEXT: s_endpgm
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28 ;
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29 ; VARIANT1-LABEL: test_barrier:
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30 ; VARIANT1: ; %bb.0: ; %entry
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31 ; VARIANT1-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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32 ; VARIANT1-NEXT: s_load_dword s2, s[0:1], 0xb
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33 ; VARIANT1-NEXT: v_not_b32_e32 v3, v0
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34 ; VARIANT1-NEXT: s_mov_b32 s7, 0xf000
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35 ; VARIANT1-NEXT: s_mov_b32 s6, 0
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36 ; VARIANT1-NEXT: v_lshlrev_b32_e32 v1, 2, v0
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37 ; VARIANT1-NEXT: v_mov_b32_e32 v2, 0
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38 ; VARIANT1-NEXT: s_waitcnt lgkmcnt(0)
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39 ; VARIANT1-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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40 ; VARIANT1-NEXT: s_barrier
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41 ; VARIANT1-NEXT: v_add_i32_e32 v3, vcc, s2, v3
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42 ; VARIANT1-NEXT: v_ashrrev_i32_e32 v4, 31, v3
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43 ; VARIANT1-NEXT: v_lshl_b64 v[3:4], v[3:4], 2
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44 ; VARIANT1-NEXT: s_waitcnt expcnt(0)
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45 ; VARIANT1-NEXT: buffer_load_dword v0, v[3:4], s[4:7], 0 addr64
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46 ; VARIANT1-NEXT: s_waitcnt vmcnt(0)
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47 ; VARIANT1-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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48 ; VARIANT1-NEXT: s_endpgm
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49 ;
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50 ; VARIANT2-LABEL: test_barrier:
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51 ; VARIANT2: ; %bb.0: ; %entry
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52 ; VARIANT2-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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53 ; VARIANT2-NEXT: s_load_dword s0, s[0:1], 0x2c
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54 ; VARIANT2-NEXT: v_lshlrev_b32_e32 v3, 2, v0
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55 ; VARIANT2-NEXT: s_waitcnt lgkmcnt(0)
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56 ; VARIANT2-NEXT: v_mov_b32_e32 v4, s3
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57 ; VARIANT2-NEXT: v_xad_u32 v1, v0, -1, s0
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58 ; VARIANT2-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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59 ; VARIANT2-NEXT: v_add_co_u32_e32 v3, vcc, s2, v3
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60 ; VARIANT2-NEXT: v_lshlrev_b64 v[1:2], 2, v[1:2]
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61 ; VARIANT2-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
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62 ; VARIANT2-NEXT: global_store_dword v[3:4], v0, off
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63 ; VARIANT2-NEXT: v_mov_b32_e32 v5, s3
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64 ; VARIANT2-NEXT: v_add_co_u32_e32 v0, vcc, s2, v1
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65 ; VARIANT2-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
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66 ; VARIANT2-NEXT: s_waitcnt vmcnt(0)
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67 ; VARIANT2-NEXT: s_barrier
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68 ; VARIANT2-NEXT: global_load_dword v0, v[0:1], off
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69 ; VARIANT2-NEXT: s_waitcnt vmcnt(0)
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70 ; VARIANT2-NEXT: global_store_dword v[3:4], v0, off
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71 ; VARIANT2-NEXT: s_endpgm
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72 ;
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73 ; VARIANT3-LABEL: test_barrier:
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74 ; VARIANT3: ; %bb.0: ; %entry
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75 ; VARIANT3-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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76 ; VARIANT3-NEXT: s_load_dword s0, s[0:1], 0x2c
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77 ; VARIANT3-NEXT: v_lshlrev_b32_e32 v3, 2, v0
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78 ; VARIANT3-NEXT: s_waitcnt lgkmcnt(0)
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79 ; VARIANT3-NEXT: v_mov_b32_e32 v4, s3
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80 ; VARIANT3-NEXT: v_xad_u32 v1, v0, -1, s0
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81 ; VARIANT3-NEXT: v_ashrrev_i32_e32 v2, 31, v1
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82 ; VARIANT3-NEXT: v_add_co_u32_e32 v3, vcc, s2, v3
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83 ; VARIANT3-NEXT: v_lshlrev_b64 v[1:2], 2, v[1:2]
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84 ; VARIANT3-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
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85 ; VARIANT3-NEXT: global_store_dword v[3:4], v0, off
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86 ; VARIANT3-NEXT: v_mov_b32_e32 v5, s3
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87 ; VARIANT3-NEXT: v_add_co_u32_e32 v0, vcc, s2, v1
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88 ; VARIANT3-NEXT: v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
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89 ; VARIANT3-NEXT: s_barrier
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90 ; VARIANT3-NEXT: global_load_dword v0, v[0:1], off
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91 ; VARIANT3-NEXT: s_waitcnt vmcnt(0)
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92 ; VARIANT3-NEXT: global_store_dword v[3:4], v0, off
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93 ; VARIANT3-NEXT: s_endpgm
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94 entry:
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95 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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96 %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp
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97 store i32 %tmp, i32 addrspace(1)* %tmp1
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98 call void @llvm.amdgcn.s.barrier()
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99 %tmp3 = sub i32 %size, 1
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100 %tmp4 = sub i32 %tmp3, %tmp
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101 %tmp5 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp4
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102 %tmp6 = load i32, i32 addrspace(1)* %tmp5
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103 store i32 %tmp6, i32 addrspace(1)* %tmp1
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104 ret void
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105 }
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106
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107 declare void @llvm.amdgcn.s.barrier() #1
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108 declare i32 @llvm.amdgcn.workitem.id.x() #2
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109
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110 attributes #0 = { nounwind }
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111 attributes #1 = { convergent nounwind }
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112 attributes #2 = { nounwind readnone }
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