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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
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3 ; RUN: llc -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM %s
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4
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5 ; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll,
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6 ; but with all 64-bit tests, and tests with loads dropped.
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7
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8 ; Patterns:
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9 ; a) x & (1 << nbits) - 1
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10 ; b) x & ~(-1 << nbits)
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11 ; c) x & (-1 >> (32 - y))
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12 ; d) x << (32 - y) >> (32 - y)
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13 ; are equivalent.
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14
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15 ; ---------------------------------------------------------------------------- ;
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16 ; Pattern a. 32-bit
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17 ; ---------------------------------------------------------------------------- ;
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18
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19 define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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20 ; EG-LABEL: bzhi32_a0:
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21 ; EG: ; %bb.0:
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22 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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23 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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24 ; EG-NEXT: CF_END
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25 ; EG-NEXT: PAD
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26 ; EG-NEXT: ALU clause starting at 4:
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27 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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28 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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29 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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30 ;
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31 ; CM-LABEL: bzhi32_a0:
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32 ; CM: ; %bb.0:
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33 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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34 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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35 ; CM-NEXT: CF_END
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36 ; CM-NEXT: PAD
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37 ; CM-NEXT: ALU clause starting at 4:
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38 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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39 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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40 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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41 %onebit = shl i32 1, %numlowbits
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42 %mask = add nsw i32 %onebit, -1
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43 %masked = and i32 %mask, %val
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44 store i32 %masked, i32 addrspace(1)* %out
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45 ret void
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46 }
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47
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48 define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
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49 ; EG-LABEL: bzhi32_a1_indexzext:
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50 ; EG: ; %bb.0:
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51 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
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52 ; EG-NEXT: TEX 0 @6
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53 ; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
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54 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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55 ; EG-NEXT: CF_END
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56 ; EG-NEXT: PAD
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57 ; EG-NEXT: Fetch clause starting at 6:
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58 ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
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59 ; EG-NEXT: ALU clause starting at 8:
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60 ; EG-NEXT: MOV * T0.X, 0.0,
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61 ; EG-NEXT: ALU clause starting at 9:
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62 ; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
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63 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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64 ; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W,
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65 ; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
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66 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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67 ;
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68 ; CM-LABEL: bzhi32_a1_indexzext:
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69 ; CM: ; %bb.0:
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70 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
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71 ; CM-NEXT: TEX 0 @6
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72 ; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
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73 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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74 ; CM-NEXT: CF_END
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75 ; CM-NEXT: PAD
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76 ; CM-NEXT: Fetch clause starting at 6:
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77 ; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
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78 ; CM-NEXT: ALU clause starting at 8:
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79 ; CM-NEXT: MOV * T0.X, 0.0,
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80 ; CM-NEXT: ALU clause starting at 9:
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81 ; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
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82 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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83 ; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W,
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84 ; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
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85 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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86 %conv = zext i8 %numlowbits to i32
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87 %onebit = shl i32 1, %conv
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88 %mask = add nsw i32 %onebit, -1
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89 %masked = and i32 %mask, %val
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90 store i32 %masked, i32 addrspace(1)* %out
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91 ret void
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92 }
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93
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94 define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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95 ; EG-LABEL: bzhi32_a4_commutative:
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96 ; EG: ; %bb.0:
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97 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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98 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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99 ; EG-NEXT: CF_END
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100 ; EG-NEXT: PAD
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101 ; EG-NEXT: ALU clause starting at 4:
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102 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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103 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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104 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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105 ;
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106 ; CM-LABEL: bzhi32_a4_commutative:
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107 ; CM: ; %bb.0:
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108 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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109 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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110 ; CM-NEXT: CF_END
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111 ; CM-NEXT: PAD
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112 ; CM-NEXT: ALU clause starting at 4:
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113 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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114 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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115 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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116 %onebit = shl i32 1, %numlowbits
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117 %mask = add nsw i32 %onebit, -1
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118 %masked = and i32 %val, %mask ; swapped order
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119 store i32 %masked, i32 addrspace(1)* %out
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120 ret void
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121 }
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122
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123 ; ---------------------------------------------------------------------------- ;
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124 ; Pattern b. 32-bit
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125 ; ---------------------------------------------------------------------------- ;
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126
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127 define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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128 ; EG-LABEL: bzhi32_b0:
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129 ; EG: ; %bb.0:
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130 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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131 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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132 ; EG-NEXT: CF_END
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133 ; EG-NEXT: PAD
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134 ; EG-NEXT: ALU clause starting at 4:
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135 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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136 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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137 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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138 ;
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139 ; CM-LABEL: bzhi32_b0:
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140 ; CM: ; %bb.0:
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141 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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142 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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143 ; CM-NEXT: CF_END
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144 ; CM-NEXT: PAD
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145 ; CM-NEXT: ALU clause starting at 4:
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146 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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147 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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148 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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149 %notmask = shl i32 -1, %numlowbits
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150 %mask = xor i32 %notmask, -1
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151 %masked = and i32 %mask, %val
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152 store i32 %masked, i32 addrspace(1)* %out
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153 ret void
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154 }
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155
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156 define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
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157 ; EG-LABEL: bzhi32_b1_indexzext:
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158 ; EG: ; %bb.0:
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159 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
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160 ; EG-NEXT: TEX 0 @6
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161 ; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
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162 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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163 ; EG-NEXT: CF_END
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164 ; EG-NEXT: PAD
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165 ; EG-NEXT: Fetch clause starting at 6:
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166 ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
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167 ; EG-NEXT: ALU clause starting at 8:
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168 ; EG-NEXT: MOV * T0.X, 0.0,
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169 ; EG-NEXT: ALU clause starting at 9:
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170 ; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
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171 ; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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172 ; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W,
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173 ; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
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174 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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175 ;
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176 ; CM-LABEL: bzhi32_b1_indexzext:
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177 ; CM: ; %bb.0:
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178 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
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179 ; CM-NEXT: TEX 0 @6
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180 ; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
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181 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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182 ; CM-NEXT: CF_END
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183 ; CM-NEXT: PAD
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184 ; CM-NEXT: Fetch clause starting at 6:
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185 ; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
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186 ; CM-NEXT: ALU clause starting at 8:
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187 ; CM-NEXT: MOV * T0.X, 0.0,
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188 ; CM-NEXT: ALU clause starting at 9:
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189 ; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,
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190 ; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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191 ; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W,
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192 ; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
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193 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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194 %conv = zext i8 %numlowbits to i32
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195 %notmask = shl i32 -1, %conv
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196 %mask = xor i32 %notmask, -1
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197 %masked = and i32 %mask, %val
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198 store i32 %masked, i32 addrspace(1)* %out
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199 ret void
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200 }
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201
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202 define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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203 ; EG-LABEL: bzhi32_b4_commutative:
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204 ; EG: ; %bb.0:
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205 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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206 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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207 ; EG-NEXT: CF_END
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208 ; EG-NEXT: PAD
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209 ; EG-NEXT: ALU clause starting at 4:
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210 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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211 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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212 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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213 ;
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214 ; CM-LABEL: bzhi32_b4_commutative:
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215 ; CM: ; %bb.0:
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216 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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217 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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218 ; CM-NEXT: CF_END
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219 ; CM-NEXT: PAD
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220 ; CM-NEXT: ALU clause starting at 4:
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221 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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222 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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223 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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224 %notmask = shl i32 -1, %numlowbits
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225 %mask = xor i32 %notmask, -1
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226 %masked = and i32 %val, %mask ; swapped order
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227 store i32 %masked, i32 addrspace(1)* %out
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228 ret void
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229 }
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230
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231 ; ---------------------------------------------------------------------------- ;
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232 ; Pattern c. 32-bit
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233 ; ---------------------------------------------------------------------------- ;
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234
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235 define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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236 ; EG-LABEL: bzhi32_c0:
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237 ; EG: ; %bb.0:
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238 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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239 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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240 ; EG-NEXT: CF_END
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241 ; EG-NEXT: PAD
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242 ; EG-NEXT: ALU clause starting at 4:
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243 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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244 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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245 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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246 ;
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247 ; CM-LABEL: bzhi32_c0:
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248 ; CM: ; %bb.0:
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249 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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250 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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251 ; CM-NEXT: CF_END
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252 ; CM-NEXT: PAD
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253 ; CM-NEXT: ALU clause starting at 4:
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254 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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255 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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256 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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257 %numhighbits = sub i32 32, %numlowbits
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258 %mask = lshr i32 -1, %numhighbits
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259 %masked = and i32 %mask, %val
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260 store i32 %masked, i32 addrspace(1)* %out
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261 ret void
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262 }
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263
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264 define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
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265 ; EG-LABEL: bzhi32_c1_indexzext:
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266 ; EG: ; %bb.0:
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267 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
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268 ; EG-NEXT: TEX 0 @6
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269 ; EG-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]
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270 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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271 ; EG-NEXT: CF_END
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272 ; EG-NEXT: PAD
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273 ; EG-NEXT: Fetch clause starting at 6:
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274 ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
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275 ; EG-NEXT: ALU clause starting at 8:
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276 ; EG-NEXT: MOV * T0.X, 0.0,
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277 ; EG-NEXT: ALU clause starting at 9:
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278 ; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X,
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279 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
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280 ; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
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281 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
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282 ; EG-NEXT: LSHR * T0.W, literal.x, PV.W,
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283 ; EG-NEXT: -1(nan), 0(0.000000e+00)
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284 ; EG-NEXT: AND_INT T0.X, PV.W, KC0[2].Y,
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285 ; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
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286 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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287 ;
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288 ; CM-LABEL: bzhi32_c1_indexzext:
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289 ; CM: ; %bb.0:
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290 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
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291 ; CM-NEXT: TEX 0 @6
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292 ; CM-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]
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293 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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294 ; CM-NEXT: CF_END
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295 ; CM-NEXT: PAD
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296 ; CM-NEXT: Fetch clause starting at 6:
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297 ; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
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298 ; CM-NEXT: ALU clause starting at 8:
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299 ; CM-NEXT: MOV * T0.X, 0.0,
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300 ; CM-NEXT: ALU clause starting at 9:
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301 ; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X,
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302 ; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)
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303 ; CM-NEXT: AND_INT * T0.W, PV.W, literal.x,
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304 ; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)
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305 ; CM-NEXT: LSHR * T0.W, literal.x, PV.W,
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306 ; CM-NEXT: -1(nan), 0(0.000000e+00)
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307 ; CM-NEXT: AND_INT * T0.X, PV.W, KC0[2].Y,
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308 ; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
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309 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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310 %numhighbits = sub i8 32, %numlowbits
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311 %sh_prom = zext i8 %numhighbits to i32
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312 %mask = lshr i32 -1, %sh_prom
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313 %masked = and i32 %mask, %val
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314 store i32 %masked, i32 addrspace(1)* %out
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315 ret void
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316 }
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317
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318 define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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319 ; EG-LABEL: bzhi32_c4_commutative:
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320 ; EG: ; %bb.0:
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321 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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322 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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323 ; EG-NEXT: CF_END
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324 ; EG-NEXT: PAD
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325 ; EG-NEXT: ALU clause starting at 4:
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326 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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327 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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328 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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329 ;
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330 ; CM-LABEL: bzhi32_c4_commutative:
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331 ; CM: ; %bb.0:
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332 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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333 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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334 ; CM-NEXT: CF_END
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335 ; CM-NEXT: PAD
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336 ; CM-NEXT: ALU clause starting at 4:
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337 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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338 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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339 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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340 %numhighbits = sub i32 32, %numlowbits
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341 %mask = lshr i32 -1, %numhighbits
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342 %masked = and i32 %val, %mask ; swapped order
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343 store i32 %masked, i32 addrspace(1)* %out
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344 ret void
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345 }
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346
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347 ; ---------------------------------------------------------------------------- ;
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348 ; Pattern d. 32-bit.
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349 ; ---------------------------------------------------------------------------- ;
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350
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351 define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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352 ; EG-LABEL: bzhi32_d0:
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353 ; EG: ; %bb.0:
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354 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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355 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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356 ; EG-NEXT: CF_END
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357 ; EG-NEXT: PAD
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358 ; EG-NEXT: ALU clause starting at 4:
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359 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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360 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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361 ; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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362 ;
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363 ; CM-LABEL: bzhi32_d0:
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364 ; CM: ; %bb.0:
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365 ; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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366 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X
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|
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367 ; CM-NEXT: CF_END
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|
|
368 ; CM-NEXT: PAD
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|
369 ; CM-NEXT: ALU clause starting at 4:
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|
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370 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,
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|
|
371 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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|
|
372 ; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,
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373 %numhighbits = sub i32 32, %numlowbits
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|
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374 %highbitscleared = shl i32 %val, %numhighbits
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|
|
375 %masked = lshr i32 %highbitscleared, %numhighbits
|
|
|
376 store i32 %masked, i32 addrspace(1)* %out
|
|
|
377 ret void
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|
|
378 }
|
|
|
379
|
|
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380 define amdgpu_kernel void @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
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|
|
381 ; EG-LABEL: bzhi32_d1_indexzext:
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|
|
382 ; EG: ; %bb.0:
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|
|
383 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
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|
|
384 ; EG-NEXT: TEX 0 @6
|
|
|
385 ; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
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|
|
386 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
|
|
387 ; EG-NEXT: CF_END
|
|
|
388 ; EG-NEXT: PAD
|
|
|
389 ; EG-NEXT: Fetch clause starting at 6:
|
|
|
390 ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
|
|
391 ; EG-NEXT: ALU clause starting at 8:
|
|
|
392 ; EG-NEXT: MOV * T0.X, 0.0,
|
|
|
393 ; EG-NEXT: ALU clause starting at 9:
|
|
|
394 ; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X,
|
|
|
395 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
|
|
396 ; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
|
|
|
397 ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
|
|
|
398 ; EG-NEXT: LSHL * T1.W, KC0[2].Y, PV.W,
|
|
|
399 ; EG-NEXT: LSHR T0.X, PV.W, T0.W,
|
|
|
400 ; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
|
|
401 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
|
|
402 ;
|
|
|
403 ; CM-LABEL: bzhi32_d1_indexzext:
|
|
|
404 ; CM: ; %bb.0:
|
|
|
405 ; CM-NEXT: ALU 0, @8, KC0[], KC1[]
|
|
|
406 ; CM-NEXT: TEX 0 @6
|
|
|
407 ; CM-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
|
|
|
408 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
|
|
|
409 ; CM-NEXT: CF_END
|
|
|
410 ; CM-NEXT: PAD
|
|
|
411 ; CM-NEXT: Fetch clause starting at 6:
|
|
|
412 ; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3
|
|
|
413 ; CM-NEXT: ALU clause starting at 8:
|
|
|
414 ; CM-NEXT: MOV * T0.X, 0.0,
|
|
|
415 ; CM-NEXT: ALU clause starting at 9:
|
|
|
416 ; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X,
|
|
|
417 ; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
|
|
418 ; CM-NEXT: AND_INT * T0.W, PV.W, literal.x,
|
|
|
419 ; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)
|
|
|
420 ; CM-NEXT: LSHL * T1.W, KC0[2].Y, PV.W,
|
|
|
421 ; CM-NEXT: LSHR * T0.X, PV.W, T0.W,
|
|
|
422 ; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,
|
|
|
423 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
|
|
424 %numhighbits = sub i8 32, %numlowbits
|
|
|
425 %sh_prom = zext i8 %numhighbits to i32
|
|
|
426 %highbitscleared = shl i32 %val, %sh_prom
|
|
|
427 %masked = lshr i32 %highbitscleared, %sh_prom
|
|
|
428 store i32 %masked, i32 addrspace(1)* %out
|
|
|
429 ret void
|
|
|
430 }
|
