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annotate llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll @ 150:1d019706d866

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LLVM10
author anatofuz
date Thu, 13 Feb 2020 15:10:13 +0900
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150
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1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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2
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3 ;CHECK: TEX
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4 ;CHECK-NEXT: ALU
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5
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6 define amdgpu_vs void @test(<4 x float> inreg %reg0) {
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7 %1 = extractelement <4 x float> %reg0, i32 0
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8 %2 = extractelement <4 x float> %reg0, i32 1
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9 %3 = extractelement <4 x float> %reg0, i32 2
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10 %4 = extractelement <4 x float> %reg0, i32 3
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11 %5 = insertelement <4 x float> undef, float %1, i32 0
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12 %6 = insertelement <4 x float> %5, float %2, i32 1
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13 %7 = insertelement <4 x float> %6, float %3, i32 2
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14 %8 = insertelement <4 x float> %7, float %4, i32 3
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15 %9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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16 %10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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17 %11 = fadd <4 x float> %9, %10
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18 call void @llvm.r600.store.swizzle(<4 x float> %11, i32 0, i32 0)
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19 ret void
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20 }
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21
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22 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
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23 declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)