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150
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1 ; RUN: opt %loadPolly -polly-scops -analyze < %s | FileCheck %s
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2 ; RUN: opt %loadPolly -polly-function-scops -analyze < %s | FileCheck %s
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3 ;
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4 ; Verify the scalar x defined in a non-affine subregion is written as it
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5 ; escapes the region. In this test the two conditionals inside the region
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6 ; are expressed as one PHI nodes with three incoming values.
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7 ;
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8 ; void f(int *A, int b) {
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9 ; for (int i = 0; i < 1024; i++) {
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10 ; int x = 0;
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11 ; if (A[i]) {
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12 ; if (b > i)
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13 ; x = 0;
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14 ; else if (b < 2 * i)
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15 ; x = i;
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16 ; else
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17 ; x = b;
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18 ; }
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19 ; A[i] = x;
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20 ; }
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21 ; }
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22
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23 ; CHECK-LABEL: Region: %bb2---%bb21
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24 ;
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25 ; CHECK: Statements {
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26 ; CHECK-NEXT: Stmt_bb3__TO__bb18
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27 ; CHECK-NEXT: Domain :=
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28 ; CHECK-NEXT: { Stmt_bb3__TO__bb18[i0] : 0 <= i0 <= 1023 };
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29 ; CHECK-NEXT: Schedule :=
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30 ; CHECK-NEXT: { Stmt_bb3__TO__bb18[i0] -> [i0, 0] };
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31 ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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32 ; CHECK-NEXT: { Stmt_bb3__TO__bb18[i0] -> MemRef_A[i0] };
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33 ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
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34 ; CHECK-NEXT: { Stmt_bb3__TO__bb18[i0] -> MemRef_x_2__phi[] };
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35 ; CHECK-NEXT: Stmt_bb18
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36 ; CHECK-NEXT: Domain :=
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37 ; CHECK-NEXT: { Stmt_bb18[i0] : 0 <= i0 <= 1023 };
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38 ; CHECK-NEXT: Schedule :=
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39 ; CHECK-NEXT: { Stmt_bb18[i0] -> [i0, 1] };
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40 ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 1]
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41 ; CHECK-NEXT: { Stmt_bb18[i0] -> MemRef_x_2__phi[] };
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42 ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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43 ; CHECK-NEXT: { Stmt_bb18[i0] -> MemRef_A[i0] };
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44 ; CHECK-NEXT: }
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45
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46 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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47
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48 define void @f(i32* %A, i32 %b) {
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49 bb:
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50 %tmp = sext i32 %b to i64
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51 %tmp1 = sext i32 %b to i64
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52 br label %bb2
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53
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54 bb2: ; preds = %bb20, %bb
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55 %indvars.iv = phi i64 [ %indvars.iv.next, %bb20 ], [ 0, %bb ]
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56 %exitcond = icmp ne i64 %indvars.iv, 1024
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57 br i1 %exitcond, label %bb3, label %bb21
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58
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59 bb3: ; preds = %bb2
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60 %tmp4 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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61 %tmp5 = load i32, i32* %tmp4, align 4
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62 %tmp6 = icmp eq i32 %tmp5, 0
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63 br i1 %tmp6, label %bb18, label %bb7
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64
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65 bb7: ; preds = %bb3
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66 %tmp8 = icmp slt i64 %indvars.iv, %tmp
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67 br i1 %tmp8, label %bb9, label %bb10
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68
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69 bb9: ; preds = %bb7
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70 br label %bb18
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71
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72 bb10: ; preds = %bb7
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73 %tmp11 = shl nsw i64 %indvars.iv, 1
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74 %tmp12 = icmp sgt i64 %tmp11, %tmp1
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75 br i1 %tmp12, label %bb13, label %bb15
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76
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77 bb13: ; preds = %bb10
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78 %tmp14 = trunc i64 %indvars.iv to i32
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79 br label %bb18
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80
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81 bb15: ; preds = %bb10
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82 br label %bb18
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83
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84 bb18: ; preds = %bb3, %bb13, %bb15, %bb9
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85 %x.2 = phi i32 [ 0, %bb9 ], [ %tmp14, %bb13 ], [ %b, %bb15 ], [ 0, %bb3 ]
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86 %tmp19 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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87 store i32 %x.2, i32* %tmp19, align 4
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88 br label %bb20
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89
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90 bb20: ; preds = %bb18
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91 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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92 br label %bb2
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93
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94 bb21: ; preds = %bb2
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95 ret void
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96 }
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