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252
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1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
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2 ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
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150
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3
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4 ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
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5 ; HSA: enable_sgpr_private_segment_buffer = 1
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6 ; HSA: enable_sgpr_dispatch_ptr = 0
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7 ; CI: enable_sgpr_queue_ptr = 1
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8 ; GFX9: enable_sgpr_queue_ptr = 0
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9
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10 ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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11 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}}
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236
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12 ; CI-DAG: s_cmp_lg_u32 [[PTR]], -1
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13 ; CI-DAG: s_cselect_b32 s[[HI:[0-9]+]], [[APERTURE]], 0
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14 ; CI-DAG: s_cselect_b32 s[[LO:[0-9]+]], [[PTR]], 0
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150
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15
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252
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16 ; GFX9-DAG: s_mov_b64 s[{{[0-9]+}}:[[HIBASE:[0-9]+]]], src_shared_base
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17
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150
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18 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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19 ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
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20
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236
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21 ; GFX9: s_cmp_lg_u32 [[PTR]], -1
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252
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22 ; GFX9-DAG: s_cselect_b32 s[[LO:[0-9]+]], s[[HIBASE]], 0
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23 ; GFX9-DAG: s_cselect_b32 s[[HI:[0-9]+]], [[PTR]], 0
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150
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24
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236
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25 ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
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150
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26
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27 ; At most 2 digits. Make sure src_shared_base is not counted as a high
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28 ; number SGPR.
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29
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236
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30 ; HSA: NumSgprs: {{[0-9]+}}
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252
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31 define amdgpu_kernel void @use_group_to_flat_addrspacecast(ptr addrspace(3) %ptr) #0 {
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32 %stof = addrspacecast ptr addrspace(3) %ptr to ptr
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33 store volatile i32 7, ptr %stof
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150
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34 ret void
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35 }
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36
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173
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37 ; Test handling inside a non-kernel
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38 ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast_func:
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236
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39 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[6:7], 0x10{{$}}
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173
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40 ; CI-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]]
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41 ; CI-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
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42 ; CI-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
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43 ; CI-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0
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44
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252
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45 ; GFX9-DAG: s_mov_b64 s[{{[0-9]+}}:[[HIBASE:[0-9]+]]], src_shared_base
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46
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173
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47 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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48
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252
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49 ; GFX9-DAG: v_mov_b32_e32 v[[VREG_HIBASE:[0-9]+]], s[[HIBASE]]
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173
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50 ; GFX9-DAG: v_cmp_ne_u32_e32 vcc, -1, v0
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51 ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, v0, vcc
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252
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52 ; GFX9-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, v[[VREG_HIBASE]], vcc
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173
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53
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236
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54 ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
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252
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55 define void @use_group_to_flat_addrspacecast_func(ptr addrspace(3) %ptr) #0 {
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56 %stof = addrspacecast ptr addrspace(3) %ptr to ptr
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57 store volatile i32 7, ptr %stof
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173
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58 ret void
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59 }
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60
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150
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61 ; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast:
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62 ; HSA: enable_sgpr_private_segment_buffer = 1
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63 ; HSA: enable_sgpr_dispatch_ptr = 0
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64 ; CI: enable_sgpr_queue_ptr = 1
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65 ; GFX9: enable_sgpr_queue_ptr = 0
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66
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67 ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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68 ; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
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69
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70 ; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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236
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71 ; CI-DAG: s_cmp_lg_u32 [[PTR]], -1
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72 ; CI-DAG: s_cselect_b32 s[[HI:[0-9]+]], [[APERTURE]], 0
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73 ; CI-DAG: s_cselect_b32 s[[LO:[0-9]+]], [[PTR]], 0
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150
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74
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75 ; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
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252
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76 ; GFX9-DAG: s_mov_b64 s[{{[0-9]+}}:[[HIBASE:[0-9]+]]], src_private_base
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150
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77
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78 ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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236
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79 ; GFX9: s_cmp_lg_u32 [[PTR]], -1
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252
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80 ; GFX9: s_cselect_b32 s[[LO:[0-9]+]], s[[HIBASE]], 0
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81 ; GFX9: s_cselect_b32 s[[HI:[0-9]+]], [[PTR]], 0
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150
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82
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236
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83 ; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
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150
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84
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236
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85 ; HSA: NumSgprs: {{[0-9]+}}
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252
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86 define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) #0 {
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87 %stof = addrspacecast ptr addrspace(5) %ptr to ptr
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88 store volatile i32 7, ptr %stof
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150
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89 ret void
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90 }
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91
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92 ; no-op
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93 ; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast:
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94 ; HSA: enable_sgpr_queue_ptr = 0
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95
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236
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96 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
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150
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97 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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98 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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99 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
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236
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100 ; HSA: flat_store_dword v[[[VPTRLO]]:[[VPTRHI]]], [[K]]
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252
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101 define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %ptr) #0 {
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102 %stof = addrspacecast ptr addrspace(1) %ptr to ptr
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103 store volatile i32 7, ptr %stof
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150
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104 ret void
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105 }
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106
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107 ; no-op
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108 ; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
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236
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109 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
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150
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110 ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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111 ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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236
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112 ; HSA: flat_load_dword v{{[0-9]+}}, v[[[VPTRLO]]:[[VPTRHI]]]
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252
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113 define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %ptr) #0 {
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114 %stof = addrspacecast ptr addrspace(4) %ptr to ptr
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115 %ld = load volatile i32, ptr %stof
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150
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116 ret void
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117 }
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118
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173
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119 ; HSA-LABEl: {{^}}use_constant_to_global_addrspacecast:
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236
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120 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]]
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221
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121 ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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122 ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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236
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123 ; CI: {{flat|global}}_load_dword v{{[0-9]+}}, v[[[VPTRLO]]:[[VPTRHI]]]
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221
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124
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125 ; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
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236
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126 ; GFX9: global_load_dword v{{[0-9]+}}, [[ZERO:v[0-9]+]], s[[[PTRLO]]:[[PTRHI]]]
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252
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127 define amdgpu_kernel void @use_constant_to_global_addrspacecast(ptr addrspace(4) %ptr) #0 {
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128 %stof = addrspacecast ptr addrspace(4) %ptr to ptr addrspace(1)
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129 %ld = load volatile i32, ptr addrspace(1) %stof
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173
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130 ret void
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131 }
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132
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150
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133 ; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast:
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134 ; HSA: enable_sgpr_private_segment_buffer = 1
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135 ; HSA: enable_sgpr_dispatch_ptr = 0
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136 ; HSA: enable_sgpr_queue_ptr = 0
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137
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236
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138 ; HSA: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]]
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139 ; CI-DAG: v_cmp_ne_u64_e64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
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140 ; CI-DAG: s_and_b64 s{{[[0-9]+:[0-9]+]}}, s[[[CMP_LO]]:[[CMP_HI]]], exec
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141 ; CI-DAG: s_cselect_b32 [[CASTPTR:s[0-9]+]], s[[PTR_LO]], -1
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142 ; CI-DAG: v_mov_b32_e32 [[VCASTPTR:v[0-9]+]], [[CASTPTR]]
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150
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143 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
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236
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144 ; GFX9-DAG: s_cmp_lg_u64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], 0
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221
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145 ; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1
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146 ; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]]
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236
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147 ; CI-DAG: ds_write_b32 [[VCASTPTR]], v[[K]]
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148 ; GFX9-DAG: ds_write_b32 [[CASTPTR]], v[[K]]
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252
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149 define amdgpu_kernel void @use_flat_to_group_addrspacecast(ptr %ptr) #0 {
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150 %ftos = addrspacecast ptr %ptr to ptr addrspace(3)
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151 store volatile i32 0, ptr addrspace(3) %ftos
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150
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152 ret void
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153 }
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154
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155 ; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast:
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156 ; HSA: enable_sgpr_private_segment_buffer = 1
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157 ; HSA: enable_sgpr_dispatch_ptr = 0
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158 ; HSA: enable_sgpr_queue_ptr = 0
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159
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236
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160 ; HSA: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]]
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161 ; CI-DAG v_cmp_ne_u64_e64 vcc, s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
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162 ; CI-DAG v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
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163 ; CI-DAG v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
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164 ; CI-DAG: v_cmp_ne_u64_e64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], s[[[PTR_LO]]:[[PTR_HI]]], 0{{$}}
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165 ; CI-DAG: s_and_b64 s{{[[0-9]+:[0-9]+]}}, s[[[CMP_LO]]:[[CMP_HI]]], exec
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166 ; CI-DAG: s_cselect_b32 [[CASTPTR:s[0-9]+]], s[[PTR_LO]], -1
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167 ; CI-DAG: v_mov_b32_e32 [[VCASTPTR:v[0-9]+]], [[CASTPTR]]
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150
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168 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
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236
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169 ; GFX9-DAG: s_cmp_lg_u64 s[[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]], 0
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221
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170 ; GFX9-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1
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171 ; GFX9-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]]
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236
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172 ; CI: buffer_store_dword v[[K]], [[VCASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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173 ; GFX9: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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252
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174 define amdgpu_kernel void @use_flat_to_private_addrspacecast(ptr %ptr) #0 {
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175 %ftos = addrspacecast ptr %ptr to ptr addrspace(5)
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176 store volatile i32 0, ptr addrspace(5) %ftos
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150
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177 ret void
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178 }
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179
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180 ; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast:
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181 ; HSA: enable_sgpr_queue_ptr = 0
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182
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236
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183 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]], s[4:5], 0x0
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221
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184 ; CI-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
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185 ; CI-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
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186 ; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0
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236
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187 ; CI: flat_store_dword v[[[VPTRLO]]:[[VPTRHI]]], [[K]]
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221
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188
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189 ; GFX9: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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236
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190 ; GFX9: global_store_dword [[ZERO]], [[ZERO]], s[[[PTRLO]]:[[PTRHI]]{{\]$}}
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252
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191 define amdgpu_kernel void @use_flat_to_global_addrspacecast(ptr %ptr) #0 {
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192 %ftos = addrspacecast ptr %ptr to ptr addrspace(1)
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193 store volatile i32 0, ptr addrspace(1) %ftos
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150
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194 ret void
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195 }
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196
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197 ; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast:
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198 ; HSA: enable_sgpr_queue_ptr = 0
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199
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236
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200 ; HSA: s_load_dwordx2 s[[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]], s[4:5], 0x0
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201 ; HSA: s_load_dword s{{[0-9]+}}, s[[[PTRLO]]:[[PTRHI]]], 0x0
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252
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202 define amdgpu_kernel void @use_flat_to_constant_addrspacecast(ptr %ptr) #0 {
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203 %ftos = addrspacecast ptr %ptr to ptr addrspace(4)
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204 load volatile i32, ptr addrspace(4) %ftos
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150
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205 ret void
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206 }
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207
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208 ; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast:
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209 ; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
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210 ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
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211
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252
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212 ; GFX9-DAG: s_mov_b64 s[{{[0-9]+}}:[[HI:[0-9]+]]], src_shared_base
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150
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213
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214 ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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215 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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236
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216 ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
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150
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217 define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 {
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252
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218 %cast = addrspacecast ptr addrspace(3) null to ptr
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219 store volatile i32 7, ptr %cast
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150
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220 ret void
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221 }
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222
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223 ; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast:
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224 ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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225 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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226 ; HSA: ds_write_b32 [[PTR]], [[K]]
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227 define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 {
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252
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228 %cast = addrspacecast ptr null to ptr addrspace(3)
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229 store volatile i32 7, ptr addrspace(3) %cast
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150
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230 ret void
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231 }
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232
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233 ; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast:
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234 ; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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223
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235 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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236 ; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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236
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237 ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
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150
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238 define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 {
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252
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239 %cast = addrspacecast ptr addrspace(3) inttoptr (i32 -1 to ptr addrspace(3)) to ptr
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240 store volatile i32 7, ptr %cast
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150
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241 ret void
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242 }
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243
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244 ; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast:
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245 ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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246 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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247 ; HSA: ds_write_b32 [[PTR]], [[K]]
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248 define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 {
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252
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249 %cast = addrspacecast ptr inttoptr (i64 -1 to ptr) to ptr addrspace(3)
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250 store volatile i32 7, ptr addrspace(3) %cast
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150
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251 ret void
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252 }
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253
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254 ; FIXME: Shouldn't need to enable queue ptr
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255 ; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast:
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221
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256 ; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11
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257 ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
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258
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252
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259 ; GFX9-DAG: s_mov_b64 s[{{[0-9]+}}:[[HI:[0-9]+]]], src_private_base
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150
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260
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261 ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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262 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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236
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263 ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
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150
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264 define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
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252
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265 %cast = addrspacecast ptr addrspace(5) null to ptr
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266 store volatile i32 7, ptr %cast
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150
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267 ret void
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268 }
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269
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270 ; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast:
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221
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271 ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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272 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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273 ; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0
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150
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274 define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
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252
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275 %cast = addrspacecast ptr null to ptr addrspace(5)
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276 store volatile i32 7, ptr addrspace(5) %cast
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150
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277 ret void
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278 }
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279
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221
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280
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281 ; HSA-LABEL: {{^}}cast_neg1_private_to_flat_addrspacecast:
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282 ; CI: enable_sgpr_queue_ptr = 1
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283 ; GFX9: enable_sgpr_queue_ptr = 0
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284
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223
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285 ; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
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221
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286 ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
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223
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287 ; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
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236
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288 ; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]
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221
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289 define amdgpu_kernel void @cast_neg1_private_to_flat_addrspacecast() #0 {
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252
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290 %cast = addrspacecast ptr addrspace(5) inttoptr (i32 -1 to ptr addrspace(5)) to ptr
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291 store volatile i32 7, ptr %cast
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221
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292 ret void
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293 }
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294
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295 ; HSA-LABEL: {{^}}cast_neg1_flat_to_private_addrspacecast:
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296 ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
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297 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
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298 ; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, 0
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|
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299 define amdgpu_kernel void @cast_neg1_flat_to_private_addrspacecast() #0 {
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252
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300 %cast = addrspacecast ptr inttoptr (i64 -1 to ptr) to ptr addrspace(5)
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301 store volatile i32 7, ptr addrspace(5) %cast
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221
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302 ret void
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303 }
|
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304
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305
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|
150
|
306 ; Disable optimizations in case there are optimizations added that
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307 ; specialize away generic pointer accesses.
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308
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309 ; HSA-LABEL: {{^}}branch_use_flat_i32:
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310 ; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}
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311 ; HSA: s_endpgm
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252
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312 define amdgpu_kernel void @branch_use_flat_i32(ptr addrspace(1) noalias %out, ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, i32 %x, i32 %c) #0 {
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|
150
|
313 entry:
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|
314 %cmp = icmp ne i32 %c, 0
|
|
|
315 br i1 %cmp, label %local, label %global
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316
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317 local:
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252
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318 %flat_local = addrspacecast ptr addrspace(3) %lptr to ptr
|
|
150
|
319 br label %end
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320
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321 global:
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252
|
322 %flat_global = addrspacecast ptr addrspace(1) %gptr to ptr
|
|
150
|
323 br label %end
|
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324
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325 end:
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252
|
326 %fptr = phi ptr [ %flat_local, %local ], [ %flat_global, %global ]
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327 store volatile i32 %x, ptr %fptr, align 4
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328 ; %val = load i32, ptr %fptr, align 4
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329 ; store i32 %val, ptr addrspace(1) %out, align 4
|
|
150
|
330 ret void
|
|
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331 }
|
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332
|
|
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333 ; Check for prologue initializing special SGPRs pointing to scratch.
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334 ; HSA-LABEL: {{^}}store_flat_scratch:
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335 ; CI-DAG: s_mov_b32 flat_scratch_lo, s9
|
|
223
|
336 ; CI-DAG: s_add_i32 [[ADD:s[0-9]+]], s8, s11
|
|
221
|
337 ; CI-DAG: s_lshr_b32 flat_scratch_hi, [[ADD]], 8
|
|
150
|
338
|
|
|
339 ; GFX9: s_add_u32 flat_scratch_lo, s6, s9
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|
|
340 ; GFX9: s_addc_u32 flat_scratch_hi, s7, 0
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|
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341
|
|
|
342 ; HSA: {{flat|global}}_store_dword
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|
|
343 ; HSA: s_barrier
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|
|
344 ; HSA: {{flat|global}}_load_dword
|
|
252
|
345 define amdgpu_kernel void @store_flat_scratch(ptr addrspace(1) noalias %out, i32) #0 {
|
|
150
|
346 %alloca = alloca i32, i32 9, align 4, addrspace(5)
|
|
|
347 %x = call i32 @llvm.amdgcn.workitem.id.x() #2
|
|
252
|
348 %pptr = getelementptr i32, ptr addrspace(5) %alloca, i32 %x
|
|
|
349 %fptr = addrspacecast ptr addrspace(5) %pptr to ptr
|
|
|
350 store volatile i32 %x, ptr %fptr
|
|
150
|
351 ; Dummy call
|
|
|
352 call void @llvm.amdgcn.s.barrier() #1
|
|
252
|
353 %reload = load volatile i32, ptr %fptr, align 4
|
|
|
354 store volatile i32 %reload, ptr addrspace(1) %out, align 4
|
|
150
|
355 ret void
|
|
|
356 }
|
|
|
357
|
|
173
|
358 ; HSA-LABEL: {{^}}use_constant_to_constant32_addrspacecast
|
|
|
359 ; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
|
|
|
360 ; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
|
|
236
|
361 ; GFX9: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], [[PTRPTR]], 0x0{{$}}
|
|
173
|
362 ; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
|
|
|
363 ; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
|
|
236
|
364 ; GFX9: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x0{{$}}
|
|
252
|
365 define amdgpu_kernel void @use_constant_to_constant32_addrspacecast(ptr addrspace(4) %ptr.ptr, i32 %offset) #0 {
|
|
|
366 %ptr = load volatile ptr addrspace(4), ptr addrspace(4) %ptr.ptr
|
|
|
367 %addrspacecast = addrspacecast ptr addrspace(4) %ptr to ptr addrspace(6)
|
|
|
368 %gep = getelementptr i8, ptr addrspace(6) %addrspacecast, i32 %offset
|
|
|
369 %load = load volatile i32, ptr addrspace(6) %gep, align 4
|
|
173
|
370 ret void
|
|
|
371 }
|
|
|
372
|
|
|
373 ; HSA-LABEL: {{^}}use_global_to_constant32_addrspacecast
|
|
|
374 ; GFX9: s_load_dwordx2 [[PTRPTR:s\[[0-9]+:[0-9]+\]]], s[4:5], 0x0{{$}}
|
|
|
375 ; GFX9: s_load_dword [[OFFSET:s[0-9]+]], s[4:5], 0x8{{$}}
|
|
236
|
376 ; GFX9: s_load_dwordx2 s[[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]], [[PTRPTR]], 0x0{{$}}
|
|
173
|
377 ; GFX9: s_mov_b32 s[[PTR_HI]], 0{{$}}
|
|
|
378 ; GFX9: s_add_i32 s[[PTR_LO]], s[[PTR_LO]], [[OFFSET]]
|
|
236
|
379 ; GFX9: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]], 0x0{{$}}
|
|
252
|
380 define amdgpu_kernel void @use_global_to_constant32_addrspacecast(ptr addrspace(4) %ptr.ptr, i32 %offset) #0 {
|
|
|
381 %ptr = load volatile ptr addrspace(1), ptr addrspace(4) %ptr.ptr
|
|
|
382 %addrspacecast = addrspacecast ptr addrspace(1) %ptr to ptr addrspace(6)
|
|
|
383 %gep = getelementptr i8, ptr addrspace(6) %addrspacecast, i32 %offset
|
|
|
384 %load = load volatile i32, ptr addrspace(6) %gep, align 4
|
|
173
|
385 ret void
|
|
|
386 }
|
|
|
387
|
|
236
|
388 ; GCN-LABEL: {{^}}use_constant32bit_to_flat_addrspacecast_0:
|
|
|
389 ; GCN: s_load_dword [[PTR:s[0-9]+]],
|
|
|
390 ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0
|
|
|
391 ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], [[PTR]]
|
|
|
392 ; GCN: flat_load_dword v{{[0-9]+}}, v[[[LO]]:[[HI]]]
|
|
252
|
393 define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast_0(ptr addrspace(6) %ptr) #0 {
|
|
|
394 %stof = addrspacecast ptr addrspace(6) %ptr to ptr
|
|
|
395 %load = load volatile i32, ptr %stof
|
|
236
|
396 ret void
|
|
|
397 }
|
|
|
398
|
|
|
399 ; GCN-LABEL: {{^}}use_constant32bit_to_flat_addrspacecast_1:
|
|
|
400 ; GCN: s_load_dword [[PTR:s[0-9]+]],
|
|
|
401 ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], 0xffff8000
|
|
|
402 ; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], [[PTR]]
|
|
|
403 ; GCN: flat_load_dword v{{[0-9]+}}, v[[[LO]]:[[HI]]]
|
|
252
|
404 define amdgpu_kernel void @use_constant32bit_to_flat_addrspacecast_1(ptr addrspace(6) %ptr) #3 {
|
|
|
405 %stof = addrspacecast ptr addrspace(6) %ptr to ptr
|
|
|
406 %load = load volatile i32, ptr %stof
|
|
236
|
407 ret void
|
|
|
408 }
|
|
|
409
|
|
150
|
410 declare void @llvm.amdgcn.s.barrier() #1
|
|
|
411 declare i32 @llvm.amdgcn.workitem.id.x() #2
|
|
|
412
|
|
|
413 attributes #0 = { nounwind }
|
|
|
414 attributes #1 = { nounwind convergent }
|
|
|
415 attributes #2 = { nounwind readnone }
|
|
236
|
416 attributes #3 = { nounwind "amdgpu-32bit-address-high-bits"="0xffff8000" }
|
|
252
|
417
|
|
|
418 !llvm.module.flags = !{!0}
|
|
|
419 !0 = !{i32 1, !"amdgpu_code_object_version", i32 200}
|
