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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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2 ; RUN: llc -march=amdgcn -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
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3 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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4
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5 declare float @llvm.fabs.f32(float) #1
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6 declare float @llvm.floor.f32(float) #1
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7
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8 ; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
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9 ; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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10 ; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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11 ; SI: s_endpgm
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252
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12 define amdgpu_kernel void @cvt_rpi_i32_f32(ptr addrspace(1) %out, float %x) #0 {
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150
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13 %fadd = fadd float %x, 0.5
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14 %floor = call float @llvm.floor.f32(float %fadd) #1
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15 %cvt = fptosi float %floor to i32
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252
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16 store i32 %cvt, ptr addrspace(1) %out
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150
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17 ret void
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18 }
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19
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20 ; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
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21 ; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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22 ; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
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23 ; SI: s_endpgm
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252
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24 define amdgpu_kernel void @cvt_rpi_i32_f32_fabs(ptr addrspace(1) %out, float %x) #0 {
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150
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25 %x.fabs = call float @llvm.fabs.f32(float %x) #1
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26 %fadd = fadd float %x.fabs, 0.5
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27 %floor = call float @llvm.floor.f32(float %fadd) #1
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28 %cvt = fptosi float %floor to i32
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252
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29 store i32 %cvt, ptr addrspace(1) %out
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150
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30 ret void
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31 }
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32
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33 ; FIXME: This doesn't work because it forms fsub 0.5, x
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34 ; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
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35 ; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
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36 ; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
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37 ; SI-SAFE-NOT: v_cvt_flr_i32_f32
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38 ; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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39 ; SI: s_endpgm
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252
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40 define amdgpu_kernel void @cvt_rpi_i32_f32_fneg(ptr addrspace(1) %out, float %x) #0 {
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150
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41 %x.fneg = fsub float -0.000000e+00, %x
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42 %fadd = fadd float %x.fneg, 0.5
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43 %floor = call float @llvm.floor.f32(float %fadd) #1
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44 %cvt = fptosi float %floor to i32
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252
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45 store i32 %cvt, ptr addrspace(1) %out
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150
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46 ret void
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47 }
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48
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49 ; FIXME: This doesn't work for same reason as above
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50 ; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
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51 ; SI-SAFE-NOT: v_cvt_rpi_i32_f32
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52 ; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
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53
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54 ; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
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55 ; SI-SAFE-NOT: v_cvt_flr_i32_f32
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56 ; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
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57 ; SI: s_endpgm
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252
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58 define amdgpu_kernel void @cvt_rpi_i32_f32_fabs_fneg(ptr addrspace(1) %out, float %x) #0 {
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150
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59 %x.fabs = call float @llvm.fabs.f32(float %x) #1
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60 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
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61 %fadd = fadd float %x.fabs.fneg, 0.5
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62 %floor = call float @llvm.floor.f32(float %fadd) #1
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63 %cvt = fptosi float %floor to i32
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252
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64 store i32 %cvt, ptr addrspace(1) %out
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150
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65 ret void
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66 }
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67
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68 ; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:
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69 ; SI-NOT: v_cvt_rpi_i32_f32
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70 ; SI: v_add_f32
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71 ; SI: v_floor_f32
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72 ; SI: v_cvt_u32_f32
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73 ; SI: s_endpgm
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252
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74 define amdgpu_kernel void @no_cvt_rpi_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {
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150
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75 %fadd = fadd float %x, 0.5
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76 %floor = call float @llvm.floor.f32(float %fadd) #1
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77 %cvt = fptoui float %floor to i32
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252
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78 store i32 %cvt, ptr addrspace(1) %out
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150
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79 ret void
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80 }
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81
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82 attributes #0 = { nounwind }
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83 attributes #1 = { nounwind readnone }
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