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252
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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2 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=GFX68,VERDE %s
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3 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GFX68,GFX8 %s
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4 ; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
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150
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5
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6 define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
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252
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7 ; GFX68-LABEL: buffer_store:
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8 ; GFX68: ; %bb.0: ; %main_body
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9 ; GFX68-NEXT: v_mov_b32_e32 v12, 0
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10 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v12, s[0:3], 0 idxen
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11 ; GFX68-NEXT: buffer_store_dwordx4 v[4:7], v12, s[0:3], 0 idxen glc
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12 ; GFX68-NEXT: buffer_store_dwordx4 v[8:11], v12, s[0:3], 0 idxen slc
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13 ; GFX68-NEXT: s_endpgm
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14 ;
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15 ; GFX11-LABEL: buffer_store:
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16 ; GFX11: ; %bb.0: ; %main_body
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17 ; GFX11-NEXT: v_mov_b32_e32 v12, 0
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18 ; GFX11-NEXT: s_clause 0x2
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19 ; GFX11-NEXT: buffer_store_b128 v[0:3], v12, s[0:3], 0 idxen
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20 ; GFX11-NEXT: buffer_store_b128 v[4:7], v12, s[0:3], 0 idxen glc
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21 ; GFX11-NEXT: buffer_store_b128 v[8:11], v12, s[0:3], 0 idxen slc
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22 ; GFX11-NEXT: s_nop 0
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23 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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24 ; GFX11-NEXT: s_endpgm
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150
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25 main_body:
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26 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
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27 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
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28 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
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29 ret void
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30 }
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31
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32 define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
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252
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33 ; GFX68-LABEL: buffer_store_immoffs:
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34 ; GFX68: ; %bb.0: ; %main_body
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35 ; GFX68-NEXT: v_mov_b32_e32 v4, 0
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36 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen offset:42
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37 ; GFX68-NEXT: s_endpgm
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38 ;
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39 ; GFX11-LABEL: buffer_store_immoffs:
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40 ; GFX11: ; %bb.0: ; %main_body
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41 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
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42 ; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 idxen offset:42
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43 ; GFX11-NEXT: s_nop 0
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44 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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45 ; GFX11-NEXT: s_endpgm
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150
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46 main_body:
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47 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
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48 ret void
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49 }
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50
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51 define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) {
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252
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52 ; GFX68-LABEL: buffer_store_idx:
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53 ; GFX68: ; %bb.0: ; %main_body
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54 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
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55 ; GFX68-NEXT: s_endpgm
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56 ;
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57 ; GFX11-LABEL: buffer_store_idx:
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58 ; GFX11: ; %bb.0: ; %main_body
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59 ; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 idxen
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60 ; GFX11-NEXT: s_nop 0
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61 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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62 ; GFX11-NEXT: s_endpgm
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150
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63 main_body:
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64 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)
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65 ret void
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66 }
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67
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68 define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) {
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252
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69 ; GFX68-LABEL: buffer_store_ofs:
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70 ; GFX68: ; %bb.0: ; %main_body
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71 ; GFX68-NEXT: s_mov_b32 s4, 0
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72 ; GFX68-NEXT: v_mov_b32_e32 v5, v4
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73 ; GFX68-NEXT: v_mov_b32_e32 v4, s4
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74 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
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75 ; GFX68-NEXT: s_endpgm
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76 ;
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77 ; GFX11-LABEL: buffer_store_ofs:
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78 ; GFX11: ; %bb.0: ; %main_body
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79 ; GFX11-NEXT: s_mov_b32 s4, 0
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80 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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81 ; GFX11-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, s4
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82 ; GFX11-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], 0 idxen offen
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83 ; GFX11-NEXT: s_nop 0
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84 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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85 ; GFX11-NEXT: s_endpgm
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150
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86 main_body:
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87 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i32 0, i32 0)
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88 ret void
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89 }
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90
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91 define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) {
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252
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92 ; GFX68-LABEL: buffer_store_both:
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93 ; GFX68: ; %bb.0: ; %main_body
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94 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
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95 ; GFX68-NEXT: s_endpgm
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96 ;
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97 ; GFX11-LABEL: buffer_store_both:
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98 ; GFX11: ; %bb.0: ; %main_body
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99 ; GFX11-NEXT: buffer_store_b128 v[0:3], v[4:5], s[0:3], 0 idxen offen
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100 ; GFX11-NEXT: s_nop 0
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101 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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102 ; GFX11-NEXT: s_endpgm
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150
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103 main_body:
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104 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i32 0, i32 0)
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105 ret void
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106 }
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107
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108 define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) {
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252
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109 ; GFX68-LABEL: buffer_store_both_reversed:
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110 ; GFX68: ; %bb.0: ; %main_body
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111 ; GFX68-NEXT: v_mov_b32_e32 v6, v4
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112 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
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113 ; GFX68-NEXT: s_endpgm
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114 ;
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115 ; GFX11-LABEL: buffer_store_both_reversed:
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116 ; GFX11: ; %bb.0: ; %main_body
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117 ; GFX11-NEXT: v_mov_b32_e32 v6, v4
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118 ; GFX11-NEXT: buffer_store_b128 v[0:3], v[5:6], s[0:3], 0 idxen offen
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119 ; GFX11-NEXT: s_nop 0
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120 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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121 ; GFX11-NEXT: s_endpgm
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150
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122 main_body:
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123 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i32 0, i32 0)
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124 ret void
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125 }
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126
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127 ; Ideally, the register allocator would avoid the wait here
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252
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128 define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) {
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129 ; VERDE-LABEL: buffer_store_wait:
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130 ; VERDE: ; %bb.0: ; %main_body
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131 ; VERDE-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
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132 ; VERDE-NEXT: s_waitcnt expcnt(0)
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133 ; VERDE-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
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134 ; VERDE-NEXT: s_waitcnt vmcnt(0)
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135 ; VERDE-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
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136 ; VERDE-NEXT: s_endpgm
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150
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137 ;
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252
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138 ; GFX8-LABEL: buffer_store_wait:
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139 ; GFX8: ; %bb.0: ; %main_body
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140 ; GFX8-NEXT: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
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141 ; GFX8-NEXT: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
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142 ; GFX8-NEXT: s_waitcnt vmcnt(0)
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143 ; GFX8-NEXT: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
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144 ; GFX8-NEXT: s_endpgm
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145 ;
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146 ; GFX11-LABEL: buffer_store_wait:
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147 ; GFX11: ; %bb.0: ; %main_body
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148 ; GFX11-NEXT: buffer_store_b128 v[0:3], v4, s[0:3], 0 idxen
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149 ; GFX11-NEXT: buffer_load_b128 v[0:3], v5, s[0:3], 0 idxen
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150 ; GFX11-NEXT: s_waitcnt vmcnt(0)
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151 ; GFX11-NEXT: buffer_store_b128 v[0:3], v6, s[0:3], 0 idxen
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152 ; GFX11-NEXT: s_nop 0
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153 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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154 ; GFX11-NEXT: s_endpgm
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150
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155 main_body:
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156 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0)
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157 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0, i32 0)
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158 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0, i32 0)
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159 ret void
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160 }
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161
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162 define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) {
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252
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163 ; GFX68-LABEL: buffer_store_x1:
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164 ; GFX68: ; %bb.0: ; %main_body
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165 ; GFX68-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
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166 ; GFX68-NEXT: s_endpgm
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167 ;
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168 ; GFX11-LABEL: buffer_store_x1:
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169 ; GFX11: ; %bb.0: ; %main_body
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170 ; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 idxen
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171 ; GFX11-NEXT: s_nop 0
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172 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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173 ; GFX11-NEXT: s_endpgm
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150
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174 main_body:
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175 call void @llvm.amdgcn.struct.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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176 ret void
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177 }
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178
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179 define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 {
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252
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180 ; GFX68-LABEL: buffer_store_x2:
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181 ; GFX68: ; %bb.0: ; %main_body
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182 ; GFX68-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
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183 ; GFX68-NEXT: s_endpgm
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184 ;
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185 ; GFX11-LABEL: buffer_store_x2:
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186 ; GFX11: ; %bb.0: ; %main_body
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187 ; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 idxen
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188 ; GFX11-NEXT: s_nop 0
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189 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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190 ; GFX11-NEXT: s_endpgm
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150
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191 main_body:
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192 call void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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193 ret void
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194 }
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195
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196 define amdgpu_ps void @buffer_store_int(<4 x i32> inreg, <4 x i32>, <2 x i32>, i32) {
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252
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197 ; GFX68-LABEL: buffer_store_int:
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198 ; GFX68: ; %bb.0: ; %main_body
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199 ; GFX68-NEXT: v_mov_b32_e32 v7, 0
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200 ; GFX68-NEXT: buffer_store_dwordx4 v[0:3], v7, s[0:3], 0 idxen
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201 ; GFX68-NEXT: buffer_store_dwordx2 v[4:5], v7, s[0:3], 0 idxen glc
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202 ; GFX68-NEXT: buffer_store_dword v6, v7, s[0:3], 0 idxen slc
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203 ; GFX68-NEXT: s_endpgm
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204 ;
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205 ; GFX11-LABEL: buffer_store_int:
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206 ; GFX11: ; %bb.0: ; %main_body
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207 ; GFX11-NEXT: v_mov_b32_e32 v7, 0
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208 ; GFX11-NEXT: s_clause 0x2
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209 ; GFX11-NEXT: buffer_store_b128 v[0:3], v7, s[0:3], 0 idxen
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210 ; GFX11-NEXT: buffer_store_b64 v[4:5], v7, s[0:3], 0 idxen glc
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211 ; GFX11-NEXT: buffer_store_b32 v6, v7, s[0:3], 0 idxen slc
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212 ; GFX11-NEXT: s_nop 0
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213 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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214 ; GFX11-NEXT: s_endpgm
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150
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215 main_body:
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216 call void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
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217 call void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
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218 call void @llvm.amdgcn.struct.buffer.store.i32(i32 %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
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219 ret void
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220 }
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221
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222 define amdgpu_ps void @struct_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1, i32 %index) {
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252
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223 ; GFX68-LABEL: struct_buffer_store_byte:
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224 ; GFX68: ; %bb.0: ; %main_body
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225 ; GFX68-NEXT: v_cvt_u32_f32_e32 v0, v0
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226 ; GFX68-NEXT: buffer_store_byte v0, v1, s[0:3], 0 idxen
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227 ; GFX68-NEXT: s_endpgm
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228 ;
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229 ; GFX11-LABEL: struct_buffer_store_byte:
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230 ; GFX11: ; %bb.0: ; %main_body
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231 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
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232 ; GFX11-NEXT: buffer_store_b8 v0, v1, s[0:3], 0 idxen
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233 ; GFX11-NEXT: s_nop 0
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234 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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235 ; GFX11-NEXT: s_endpgm
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150
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236 main_body:
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237 %v2 = fptoui float %v1 to i32
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238 %v3 = trunc i32 %v2 to i8
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239 call void @llvm.amdgcn.struct.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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240 ret void
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241 }
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242
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243 define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1, i32 %index) {
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252
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244 ; GFX68-LABEL: struct_buffer_store_f16:
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245 ; GFX68: ; %bb.0:
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246 ; GFX68-NEXT: v_cvt_f16_f32_e32 v0, v0
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247 ; GFX68-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen
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248 ; GFX68-NEXT: s_endpgm
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249 ;
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250 ; GFX11-LABEL: struct_buffer_store_f16:
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251 ; GFX11: ; %bb.0:
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252 ; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
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253 ; GFX11-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 idxen
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254 ; GFX11-NEXT: s_nop 0
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255 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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256 ; GFX11-NEXT: s_endpgm
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150
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257 %v2 = fptrunc float %v1 to half
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258 call void @llvm.amdgcn.struct.buffer.store.f16(half %v2, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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259 ret void
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260 }
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261
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262 define amdgpu_ps void @struct_buffer_store_v2f16(<4 x i32> inreg %rsrc, <2 x half> %v1, i32 %index) {
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252
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263 ; VERDE-LABEL: struct_buffer_store_v2f16:
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264 ; VERDE: ; %bb.0:
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265 ; VERDE-NEXT: v_cvt_f16_f32_e32 v1, v1
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266 ; VERDE-NEXT: v_cvt_f16_f32_e32 v0, v0
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267 ; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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268 ; VERDE-NEXT: v_or_b32_e32 v0, v0, v1
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269 ; VERDE-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen
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270 ; VERDE-NEXT: s_endpgm
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271 ;
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272 ; GFX8-LABEL: struct_buffer_store_v2f16:
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273 ; GFX8: ; %bb.0:
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274 ; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
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275 ; GFX8-NEXT: s_endpgm
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276 ;
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277 ; GFX11-LABEL: struct_buffer_store_v2f16:
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278 ; GFX11: ; %bb.0:
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279 ; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 idxen
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280 ; GFX11-NEXT: s_nop 0
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281 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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282 ; GFX11-NEXT: s_endpgm
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150
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283 call void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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284 ret void
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285 }
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286
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287 define amdgpu_ps void @struct_buffer_store_v4f16(<4 x i32> inreg %rsrc, <4 x half> %v1, i32 %index) {
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252
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288 ; VERDE-LABEL: struct_buffer_store_v4f16:
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289 ; VERDE: ; %bb.0:
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290 ; VERDE-NEXT: v_cvt_f16_f32_e32 v3, v3
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291 ; VERDE-NEXT: v_cvt_f16_f32_e32 v2, v2
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292 ; VERDE-NEXT: v_cvt_f16_f32_e32 v5, v1
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293 ; VERDE-NEXT: v_cvt_f16_f32_e32 v0, v0
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294 ; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v3
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295 ; VERDE-NEXT: v_or_b32_e32 v1, v2, v1
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296 ; VERDE-NEXT: v_lshlrev_b32_e32 v2, 16, v5
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297 ; VERDE-NEXT: v_or_b32_e32 v0, v0, v2
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298 ; VERDE-NEXT: buffer_store_dwordx2 v[0:1], v4, s[0:3], 0 idxen
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299 ; VERDE-NEXT: s_endpgm
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300 ;
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301 ; GFX8-LABEL: struct_buffer_store_v4f16:
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302 ; GFX8: ; %bb.0:
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303 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
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304 ; GFX8-NEXT: s_endpgm
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305 ;
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306 ; GFX11-LABEL: struct_buffer_store_v4f16:
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307 ; GFX11: ; %bb.0:
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308 ; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 idxen
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309 ; GFX11-NEXT: s_nop 0
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310 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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311 ; GFX11-NEXT: s_endpgm
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150
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312 call void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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313 ret void
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314 }
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315
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316 define amdgpu_ps void @struct_buffer_store_i16(<4 x i32> inreg %rsrc, float %v1, i32 %index) {
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252
|
317 ; GFX68-LABEL: struct_buffer_store_i16:
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318 ; GFX68: ; %bb.0: ; %main_body
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319 ; GFX68-NEXT: v_cvt_u32_f32_e32 v0, v0
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320 ; GFX68-NEXT: buffer_store_short v0, v1, s[0:3], 0 idxen
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|
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321 ; GFX68-NEXT: s_endpgm
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322 ;
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|
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323 ; GFX11-LABEL: struct_buffer_store_i16:
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324 ; GFX11: ; %bb.0: ; %main_body
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325 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
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326 ; GFX11-NEXT: buffer_store_b16 v0, v1, s[0:3], 0 idxen
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327 ; GFX11-NEXT: s_nop 0
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|
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328 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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|
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329 ; GFX11-NEXT: s_endpgm
|
|
150
|
330 main_body:
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331 %v2 = fptoui float %v1 to i32
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332 %v3 = trunc i32 %v2 to i16
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333 call void @llvm.amdgcn.struct.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
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334 ret void
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335 }
|
|
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336
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337 define amdgpu_ps void @struct_buffer_store_vif16(<4 x i32> inreg %rsrc, <2 x i16> %v1, i32 %index) {
|
|
252
|
338 ; VERDE-LABEL: struct_buffer_store_vif16:
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339 ; VERDE: ; %bb.0:
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340 ; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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|
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341 ; VERDE-NEXT: v_and_b32_e32 v0, 0xffff, v0
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|
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342 ; VERDE-NEXT: v_or_b32_e32 v0, v0, v1
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|
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343 ; VERDE-NEXT: buffer_store_dword v0, v2, s[0:3], 0 idxen
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|
|
344 ; VERDE-NEXT: s_endpgm
|
|
|
345 ;
|
|
|
346 ; GFX8-LABEL: struct_buffer_store_vif16:
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|
|
347 ; GFX8: ; %bb.0:
|
|
|
348 ; GFX8-NEXT: buffer_store_dword v0, v1, s[0:3], 0 idxen
|
|
|
349 ; GFX8-NEXT: s_endpgm
|
|
|
350 ;
|
|
|
351 ; GFX11-LABEL: struct_buffer_store_vif16:
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|
|
352 ; GFX11: ; %bb.0:
|
|
|
353 ; GFX11-NEXT: buffer_store_b32 v0, v1, s[0:3], 0 idxen
|
|
|
354 ; GFX11-NEXT: s_nop 0
|
|
|
355 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
|
356 ; GFX11-NEXT: s_endpgm
|
|
150
|
357 call void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
|
|
|
358 ret void
|
|
|
359 }
|
|
|
360
|
|
|
361 define amdgpu_ps void @struct_buffer_store_v4i16(<4 x i32> inreg %rsrc, <4 x i16> %v1, i32 %index) {
|
|
252
|
362 ; VERDE-LABEL: struct_buffer_store_v4i16:
|
|
|
363 ; VERDE: ; %bb.0:
|
|
|
364 ; VERDE-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
|
365 ; VERDE-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
|
366 ; VERDE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
|
367 ; VERDE-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
|
368 ; VERDE-NEXT: v_or_b32_e32 v2, v2, v3
|
|
|
369 ; VERDE-NEXT: v_or_b32_e32 v1, v0, v1
|
|
|
370 ; VERDE-NEXT: buffer_store_dwordx2 v[1:2], v4, s[0:3], 0 idxen
|
|
|
371 ; VERDE-NEXT: s_endpgm
|
|
|
372 ;
|
|
|
373 ; GFX8-LABEL: struct_buffer_store_v4i16:
|
|
|
374 ; GFX8: ; %bb.0:
|
|
|
375 ; GFX8-NEXT: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
|
|
|
376 ; GFX8-NEXT: s_endpgm
|
|
|
377 ;
|
|
|
378 ; GFX11-LABEL: struct_buffer_store_v4i16:
|
|
|
379 ; GFX11: ; %bb.0:
|
|
|
380 ; GFX11-NEXT: buffer_store_b64 v[0:1], v2, s[0:3], 0 idxen
|
|
|
381 ; GFX11-NEXT: s_nop 0
|
|
|
382 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
|
383 ; GFX11-NEXT: s_endpgm
|
|
150
|
384 call void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0)
|
|
|
385 ret void
|
|
|
386 }
|
|
|
387
|
|
|
388 declare void @llvm.amdgcn.struct.buffer.store.f32(float, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
389 declare void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
390 declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
391 declare void @llvm.amdgcn.struct.buffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
392 declare void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
393 declare void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
394 declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #1
|
|
|
395 declare void @llvm.amdgcn.struct.buffer.store.i8(i8, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
396 declare void @llvm.amdgcn.struct.buffer.store.i16(i16, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
397 declare void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
398 declare void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
399 declare void @llvm.amdgcn.struct.buffer.store.f16(half, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
400 declare void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
401 declare void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32) #0
|
|
|
402
|
|
|
403 attributes #0 = { nounwind }
|
|
|
404 attributes #1 = { nounwind readonly }
|
