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221
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1 ; RUN: llc -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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150
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2 ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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3
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4 ; FIXME: None of these trigger madmk emission anymore. It is still
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5 ; possible, but requires the correct registers to be used which is
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6 ; hard to trigger.
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7
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8 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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9 declare float @llvm.fabs.f32(float) nounwind readnone
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10
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11 ; GCN-LABEL: {{^}}madmk_f32:
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221
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12 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
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150
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13 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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14 ; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]
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252
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15 define amdgpu_kernel void @madmk_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
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150
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16 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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17 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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18 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
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19 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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20
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21 %a = load volatile float, ptr addrspace(1) %gep.0, align 4
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22 %b = load volatile float, ptr addrspace(1) %gep.1, align 4
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23
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24 %mul = fmul float %a, 10.0
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25 %madmk = fadd float %mul, %b
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26 store float %madmk, ptr addrspace(1) %out.gep, align 4
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27 ret void
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28 }
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29
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30 ; GCN-LABEL: {{^}}madmk_2_use_f32:
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221
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31 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
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32 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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33 ; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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236
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34 ; GCN-DAG: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]
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35 ; GCN-DAG: v_mac_f32_e32 [[VC]], 0x41200000, [[VA]]
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150
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36 ; GCN: s_endpgm
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252
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37 define amdgpu_kernel void @madmk_2_use_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
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38 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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39
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40 %in.gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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41 %in.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 1
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42 %in.gep.2 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 2
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43
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44 %out.gep.0 = getelementptr float, ptr addrspace(1) %out, i32 %tid
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45 %out.gep.1 = getelementptr float, ptr addrspace(1) %in.gep.0, i32 1
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46
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47 %a = load volatile float, ptr addrspace(1) %in.gep.0, align 4
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48 %b = load volatile float, ptr addrspace(1) %in.gep.1, align 4
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49 %c = load volatile float, ptr addrspace(1) %in.gep.2, align 4
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50
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51 %mul0 = fmul float %a, 10.0
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52 %mul1 = fmul float %a, 10.0
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53 %madmk0 = fadd float %mul0, %b
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54 %madmk1 = fadd float %mul1, %c
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55
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56 store float %madmk0, ptr addrspace(1) %out.gep.0, align 4
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57 store float %madmk1, ptr addrspace(1) %out.gep.1, align 4
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58 ret void
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59 }
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60
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61 ; We don't get any benefit if the constant is an inline immediate.
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62 ; GCN-LABEL: {{^}}madmk_inline_imm_f32:
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221
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63 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
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64 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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65 ; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]]
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252
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66 define amdgpu_kernel void @madmk_inline_imm_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
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67 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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68 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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69 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
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70 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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71
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72 %a = load volatile float, ptr addrspace(1) %gep.0, align 4
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73 %b = load volatile float, ptr addrspace(1) %gep.1, align 4
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74
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75 %mul = fmul float %a, 4.0
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76 %madmk = fadd float %mul, %b
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77 store float %madmk, ptr addrspace(1) %out.gep, align 4
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78 ret void
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79 }
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80
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81 ; GCN-LABEL: {{^}}s_s_madmk_f32:
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82 ; GCN-NOT: v_madmk_f32
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83 ; GCN: v_mac_f32_e32
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84 ; GCN: s_endpgm
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252
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85 define amdgpu_kernel void @s_s_madmk_f32(ptr addrspace(1) noalias %out, [8 x i32], float %a, [8 x i32], float %b) #0 {
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86 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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87 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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88
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89 %mul = fmul float %a, 10.0
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90 %madmk = fadd float %mul, %b
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91 store float %madmk, ptr addrspace(1) %out.gep, align 4
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92 ret void
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93 }
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94
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95 ; GCN-LABEL: {{^}}v_s_madmk_f32:
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173
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96 ; GCN-DAG: s_load_dword [[SREG:s[0-9]+]]
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97 ; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]]
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150
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98 ; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]]
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99 ; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]]
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100 ; GCN: s_endpgm
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252
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101 define amdgpu_kernel void @v_s_madmk_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, float %b) #0 {
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102 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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103 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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104 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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105 %a = load float, ptr addrspace(1) %gep.0, align 4
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106
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107 %mul = fmul float %a, 10.0
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108 %madmk = fadd float %mul, %b
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109 store float %madmk, ptr addrspace(1) %out.gep, align 4
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110 ret void
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111 }
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112
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113 ; GCN-LABEL: {{^}}scalar_vector_madmk_f32:
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114 ; GCN-NOT: v_madmk_f32
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115 ; GCN: v_mac_f32_e32
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116 ; GCN: s_endpgm
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252
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117 define amdgpu_kernel void @scalar_vector_madmk_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, float %a) #0 {
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118 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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119 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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120 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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121 %b = load float, ptr addrspace(1) %gep.0, align 4
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122
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123 %mul = fmul float %a, 10.0
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124 %madmk = fadd float %mul, %b
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125 store float %madmk, ptr addrspace(1) %out.gep, align 4
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126 ret void
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127 }
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128
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129 ; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32:
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221
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130 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
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131 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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132 ; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
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133 ; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]]
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252
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134 define amdgpu_kernel void @no_madmk_src0_modifier_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
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135 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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136 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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137 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
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138 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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139
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140 %a = load volatile float, ptr addrspace(1) %gep.0, align 4
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141 %b = load volatile float, ptr addrspace(1) %gep.1, align 4
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142
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143 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
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144
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145 %mul = fmul float %a.fabs, 10.0
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146 %madmk = fadd float %mul, %b
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147 store float %madmk, ptr addrspace(1) %out.gep, align 4
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148 ret void
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149 }
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150
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151 ; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32:
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221
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152 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
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150
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153 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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154 ; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}|
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252
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155 define amdgpu_kernel void @no_madmk_src2_modifier_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
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156 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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157 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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158 %gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
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159 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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160
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161 %a = load volatile float, ptr addrspace(1) %gep.0, align 4
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162 %b = load volatile float, ptr addrspace(1) %gep.1, align 4
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163
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164 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
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165
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166 %mul = fmul float %a, 10.0
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167 %madmk = fadd float %mul, %b.fabs
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168 store float %madmk, ptr addrspace(1) %out.gep, align 4
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169 ret void
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170 }
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171
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172 ; GCN-LABEL: {{^}}madmk_add_inline_imm_f32:
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173 ; GCN: buffer_load_dword [[A:v[0-9]+]]
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174 ; GCN: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
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175 ; GCN: v_mad_f32 {{v[0-9]+}}, [[A]], [[SK]], 2.0
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252
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176 define amdgpu_kernel void @madmk_add_inline_imm_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
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177 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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178 %gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
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179 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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180
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181 %a = load float, ptr addrspace(1) %gep.0, align 4
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182
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183 %mul = fmul float %a, 10.0
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184 %madmk = fadd float %mul, 2.0
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185 store float %madmk, ptr addrspace(1) %out.gep, align 4
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186 ret void
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187 }
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188
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189 ; SI-LABEL: {{^}}kill_madmk_verifier_error:
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190 ; SI: s_or_b64
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191 ; SI: s_xor_b64
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192 ; SI: v_mac_f32_e32 {{v[0-9]+}}, 0x472aee8c, {{v[0-9]+}}
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173
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193 define amdgpu_kernel void @kill_madmk_verifier_error() #0 {
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194 bb:
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195 br label %bb2
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196
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197 bb1: ; preds = %bb2
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198 ret void
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199
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200 bb2: ; preds = %bb6, %bb
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201 %tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ]
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202 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
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203 %f_tid = bitcast i32 %tid to float
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204 %tmp3 = fsub float %f_tid, %tmp
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205 %tmp5 = fcmp oeq float %tmp3, 1.000000e+04
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206 br i1 %tmp5, label %bb1, label %bb6
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207
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208 bb6: ; preds = %bb2
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209 %tmp7 = fmul float %tmp, 0x40E55DD180000000
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210 %tmp8 = fadd float %tmp7, %tmp
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211 br label %bb2
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212 }
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213
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214 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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215
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173
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216 attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
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217 attributes #1 = { nounwind readnone }
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