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236
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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150
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
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3
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4 ; CHECK-LABEL: {{^}}phi1:
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5 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
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6 ; CHECK: ; %bb.1: ; %ELSE
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7 ; CHECK: s_xor_b32 s{{[0-9]}}, [[DST]]
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252
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8 define amdgpu_ps void @phi1(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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150
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9 main_body:
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252
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10 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0
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150
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11 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0)
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12 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0)
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13 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0)
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14 %tmp24 = fptosi float %tmp22 to i32
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15 %tmp25 = icmp ne i32 %tmp24, 0
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16 br i1 %tmp25, label %ENDIF, label %ELSE
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17
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18 ELSE: ; preds = %main_body
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19 %tmp26 = fsub float -0.000000e+00, %tmp21
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20 br label %ENDIF
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21
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22 ENDIF: ; preds = %ELSE, %main_body
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23 %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]
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24 %tmp27 = fadd float %temp.0, %tmp23
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25 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
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26 ret void
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27 }
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28
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29 ; Make sure this program doesn't crash
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30 ; CHECK-LABEL: {{^}}phi2:
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252
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31 define amdgpu_ps void @phi2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {
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32 main_body:
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252
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33 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0
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150
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34 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 16, i32 0)
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35 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 32, i32 0)
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36 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 36, i32 0)
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37 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 40, i32 0)
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38 %tmp25 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 48, i32 0)
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39 %tmp26 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 52, i32 0)
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40 %tmp27 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 56, i32 0)
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41 %tmp28 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 64, i32 0)
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42 %tmp29 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 68, i32 0)
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43 %tmp30 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 72, i32 0)
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44 %tmp31 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 76, i32 0)
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45 %tmp32 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 80, i32 0)
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46 %tmp33 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 84, i32 0)
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47 %tmp34 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 88, i32 0)
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48 %tmp35 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 92, i32 0)
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252
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49 %tmp37 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0
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50 %tmp39 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0
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150
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51 %i.i = extractelement <2 x i32> %arg5, i32 0
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52 %j.i = extractelement <2 x i32> %arg5, i32 1
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53 %i.f.i = bitcast i32 %i.i to float
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54 %j.f.i = bitcast i32 %j.i to float
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55 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1
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56 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1
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57 %i.i19 = extractelement <2 x i32> %arg5, i32 0
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58 %j.i20 = extractelement <2 x i32> %arg5, i32 1
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59 %i.f.i21 = bitcast i32 %i.i19 to float
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60 %j.f.i22 = bitcast i32 %j.i20 to float
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61 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #1
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62 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #1
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63 %i.i13 = extractelement <2 x i32> %arg5, i32 0
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64 %j.i14 = extractelement <2 x i32> %arg5, i32 1
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65 %i.f.i15 = bitcast i32 %i.i13 to float
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66 %j.f.i16 = bitcast i32 %j.i14 to float
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67 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #1
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68 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #1
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69 %i.i7 = extractelement <2 x i32> %arg5, i32 0
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70 %j.i8 = extractelement <2 x i32> %arg5, i32 1
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71 %i.f.i9 = bitcast i32 %i.i7 to float
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72 %j.f.i10 = bitcast i32 %j.i8 to float
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73 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #1
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74 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #1
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75 %i.i1 = extractelement <2 x i32> %arg5, i32 0
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76 %j.i2 = extractelement <2 x i32> %arg5, i32 1
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77 %i.f.i3 = bitcast i32 %i.i1 to float
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78 %j.f.i4 = bitcast i32 %j.i2 to float
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79 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #1
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80 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #1
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81 %tmp39.bc = bitcast <4 x i32> %tmp39 to <4 x i32>
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82 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i24, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i1 0, i32 0, i32 0)
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83 %tmp50 = extractelement <4 x float> %tmp1, i32 2
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84 %tmp51 = call float @llvm.fabs.f32(float %tmp50)
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85 %tmp52 = fmul float %p2.i18, %p2.i18
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86 %tmp53 = fmul float %p2.i12, %p2.i12
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87 %tmp54 = fadd float %tmp53, %tmp52
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88 %tmp55 = fmul float %p2.i6, %p2.i6
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89 %tmp56 = fadd float %tmp54, %tmp55
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90 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56)
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91 %tmp58 = fmul float %p2.i18, %tmp57
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92 %tmp59 = fmul float %p2.i12, %tmp57
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93 %tmp60 = fmul float %p2.i6, %tmp57
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94 %tmp61 = fmul float %tmp58, %tmp22
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95 %tmp62 = fmul float %tmp59, %tmp23
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96 %tmp63 = fadd float %tmp62, %tmp61
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97 %tmp64 = fmul float %tmp60, %tmp24
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98 %tmp65 = fadd float %tmp63, %tmp64
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99 %tmp66 = fsub float -0.000000e+00, %tmp25
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100 %tmp67 = fmul float %tmp65, %tmp51
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101 %tmp68 = fadd float %tmp67, %tmp66
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102 %tmp69 = fmul float %tmp26, %tmp68
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103 %tmp70 = fmul float %tmp27, %tmp68
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104 %tmp71 = call float @llvm.fabs.f32(float %tmp69)
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105 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71
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106 %tmp73 = sext i1 %tmp72 to i32
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107 %tmp74 = bitcast i32 %tmp73 to float
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108 %tmp75 = bitcast float %tmp74 to i32
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109 %tmp76 = icmp ne i32 %tmp75, 0
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110 br i1 %tmp76, label %IF, label %ENDIF
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111
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112 IF: ; preds = %main_body
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113 %tmp77 = fsub float -0.000000e+00, %tmp69
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114 %tmp78 = call float @llvm.exp2.f32(float %tmp77)
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115 %tmp79 = fsub float -0.000000e+00, %tmp78
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116 %tmp80 = fadd float 1.000000e+00, %tmp79
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117 %tmp81 = fdiv float 1.000000e+00, %tmp69
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118 %tmp82 = fmul float %tmp80, %tmp81
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119 %tmp83 = fmul float %tmp31, %tmp82
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120 br label %ENDIF
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121
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122 ENDIF: ; preds = %IF, %main_body
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123 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ]
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124 %tmp84 = call float @llvm.fabs.f32(float %tmp70)
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125 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84
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126 %tmp86 = sext i1 %tmp85 to i32
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127 %tmp87 = bitcast i32 %tmp86 to float
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128 %tmp88 = bitcast float %tmp87 to i32
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129 %tmp89 = icmp ne i32 %tmp88, 0
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130 br i1 %tmp89, label %IF25, label %ENDIF24
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131
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132 IF25: ; preds = %ENDIF
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133 %tmp90 = fsub float -0.000000e+00, %tmp70
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134 %tmp91 = call float @llvm.exp2.f32(float %tmp90)
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135 %tmp92 = fsub float -0.000000e+00, %tmp91
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136 %tmp93 = fadd float 1.000000e+00, %tmp92
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137 %tmp94 = fdiv float 1.000000e+00, %tmp70
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138 %tmp95 = fmul float %tmp93, %tmp94
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139 %tmp96 = fmul float %tmp35, %tmp95
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140 br label %ENDIF24
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141
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142 ENDIF24: ; preds = %IF25, %ENDIF
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143 %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ]
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144 %tmp97 = fmul float %tmp28, %temp4.0
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145 %tmp98 = fmul float %tmp29, %temp4.0
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146 %tmp99 = fmul float %tmp30, %temp4.0
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147 %tmp100 = fmul float %tmp32, %temp8.0
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148 %tmp101 = fadd float %tmp100, %tmp97
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149 %tmp102 = fmul float %tmp33, %temp8.0
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150 %tmp103 = fadd float %tmp102, %tmp98
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151 %tmp104 = fmul float %tmp34, %temp8.0
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152 %tmp105 = fadd float %tmp104, %tmp99
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153 %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21)
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154 %tmp107 = fsub float -0.000000e+00, %tmp101
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155 %tmp108 = fmul float %tmp107, %tmp106
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156 %tmp109 = fsub float -0.000000e+00, %tmp103
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157 %tmp110 = fmul float %tmp109, %tmp106
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158 %tmp111 = fsub float -0.000000e+00, %tmp105
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159 %tmp112 = fmul float %tmp111, %tmp106
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160 %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110)
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161 %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00)
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162 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0
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163 ret void
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164 }
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165
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166 ; We just want to make sure the program doesn't crash
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167 ; CHECK-LABEL: {{^}}loop:
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252
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168 define amdgpu_ps void @loop(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
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150
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169 main_body:
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252
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170 %tmp20 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0
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150
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171 %tmp21 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 0, i32 0)
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172 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 4, i32 0)
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173 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 8, i32 0)
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174 %tmp24 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp20, i32 12, i32 0)
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175 %tmp25 = fptosi float %tmp24 to i32
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176 %tmp26 = bitcast i32 %tmp25 to float
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177 %tmp27 = bitcast float %tmp26 to i32
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178 br label %LOOP
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179
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180 LOOP: ; preds = %ENDIF, %main_body
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181 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ]
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182 %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ]
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183 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ]
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184 %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ]
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185 %tmp28 = bitcast float %temp8.0 to i32
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186 %tmp29 = icmp sge i32 %tmp28, %tmp27
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187 %tmp30 = sext i1 %tmp29 to i32
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188 %tmp31 = bitcast i32 %tmp30 to float
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189 %tmp32 = bitcast float %tmp31 to i32
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190 %tmp33 = icmp ne i32 %tmp32, 0
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191 br i1 %tmp33, label %IF, label %ENDIF
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192
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193 IF: ; preds = %LOOP
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194 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00, i1 true, i1 true) #0
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195 ret void
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196
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197 ENDIF: ; preds = %LOOP
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198 %tmp34 = bitcast float %temp8.0 to i32
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199 %tmp35 = add i32 %tmp34, 1
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200 %tmp36 = bitcast i32 %tmp35 to float
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201 br label %LOOP
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202 }
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203
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204 ; This checks for a bug in the FixSGPRCopies pass where VReg96
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205 ; registers were being identified as an SGPR regclass which was causing
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206 ; an assertion failure.
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207
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208 ; CHECK-LABEL: {{^}}sample_v3:
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173
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209 ; CHECK: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
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210 ; CHECK: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
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236
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211 ; CHECK: s_cbranch
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150
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212
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173
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213 ; CHECK: BB{{[0-9]+_[0-9]+}}:
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214 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 11
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215 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 13
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150
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216
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236
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217 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v[[[SAMPLE_LO]]:[[SAMPLE_HI]]]
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150
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218 ; CHECK: exp
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219 ; CHECK: s_endpgm
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252
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220 define amdgpu_ps void @sample_v3(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
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150
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221 entry:
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252
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222 %tmp21 = load <4 x i32>, ptr addrspace(4) %arg, !tbaa !0
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150
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223 %tmp22 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp21, i32 16, i32 0)
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252
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224 %tmp24 = load <8 x i32>, ptr addrspace(4) %arg2, !tbaa !0
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225 %tmp26 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !0
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150
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226 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00
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227 %tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32>
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228 br i1 %tmp27, label %if, label %else
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229
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230 if: ; preds = %entry
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231 %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36D6000000000000, float 0x36DA000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0)
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232 %val.if.0 = extractelement <4 x float> %tmp1, i32 0
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233 %val.if.1 = extractelement <4 x float> %tmp1, i32 1
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234 %val.if.2 = extractelement <4 x float> %tmp1, i32 2
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235 br label %endif
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236
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237 else: ; preds = %entry
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238 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0x36C4000000000000, float 0x36CC000000000000, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i1 0, i32 0, i32 0)
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239 %val.else.0 = extractelement <4 x float> %tmp2, i32 0
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240 %val.else.1 = extractelement <4 x float> %tmp2, i32 1
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241 %val.else.2 = extractelement <4 x float> %tmp2, i32 2
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242 br label %endif
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243
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244 endif: ; preds = %else, %if
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245 %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ]
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246 %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ]
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247 %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ]
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248 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %val.0, float %val.1, float %val.2, float 0.000000e+00, i1 true, i1 true) #0
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249 ret void
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250 }
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251
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252 ; CHECK-LABEL: {{^}}copy1:
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253 ; CHECK: buffer_load_dword
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254 ; CHECK: v_add
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255 ; CHECK: s_endpgm
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252
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256 define amdgpu_kernel void @copy1(ptr addrspace(1) %out, ptr addrspace(1) %in0) {
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150
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257 entry:
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252
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258 %tmp = load float, ptr addrspace(1) %in0
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150
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259 %tmp1 = fcmp oeq float %tmp, 0.000000e+00
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260 br i1 %tmp1, label %if0, label %endif
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261
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262 if0: ; preds = %entry
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263 %tmp2 = bitcast float %tmp to i32
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264 %tmp3 = fcmp olt float %tmp, 0.000000e+00
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265 br i1 %tmp3, label %if1, label %endif
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266
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267 if1: ; preds = %if0
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268 %tmp4 = add i32 %tmp2, 1
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269 br label %endif
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270
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271 endif: ; preds = %if1, %if0, %entry
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272 %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ]
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273 %tmp6 = bitcast i32 %tmp5 to float
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252
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274 store float %tmp6, ptr addrspace(1) %out
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150
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275 ret void
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276 }
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277
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278 ; This test is just checking that we don't crash / assertion fail.
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279 ; CHECK-LABEL: {{^}}copy2:
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280 ; CHECK: s_endpgm
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252
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281 define amdgpu_ps void @copy2(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
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150
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282 entry:
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283 br label %LOOP68
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284
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285 LOOP68: ; preds = %ENDIF69, %entry
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286 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
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287 %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
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288 %g = icmp eq i32 0, %t
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289 %l = bitcast float %temp4.7 to i32
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290 br i1 %g, label %IF70, label %ENDIF69
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291
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292 IF70: ; preds = %LOOP68
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293 %q = icmp ne i32 %l, 13
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294 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00
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295 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
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296 ret void
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297
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298 ENDIF69: ; preds = %LOOP68
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299 %u = add i32 %l, %t
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300 %v = bitcast i32 %u to float
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301 %x = add i32 %t, -1
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302 br label %LOOP68
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303 }
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304
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305 ; This test checks that image_sample resource descriptors aren't loaded into
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306 ; vgprs. The verifier will fail if this happens.
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307 ; CHECK-LABEL:{{^}}sample_rsrc
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308
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309 ; CHECK: s_cmp_eq_u32
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236
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310 ; CHECK: s_cbranch_scc1 [[END:.LBB[0-9]+_[0-9]+]]
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150
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311
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236
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312 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}
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313 ; CHECK: s_endpgm
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150
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314
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315 ; [[END]]:
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236
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316 ; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
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317 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]]
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318 ; CHECK: s_branch
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252
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319 define amdgpu_ps void @sample_rsrc(ptr addrspace(4) inreg %arg, ptr addrspace(4) inreg %arg1, ptr addrspace(4) inreg %arg2, ptr addrspace(4) inreg %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
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150
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320 bb:
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252
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321 %tmp22 = load <4 x i32>, ptr addrspace(4) %arg1, !tbaa !3
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150
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322 %tmp23 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %tmp22, i32 16, i32 0)
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252
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323 %tmp26 = load <8 x i32>, ptr addrspace(4) %arg3, !tbaa !3
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324 %tmp28 = load <4 x i32>, ptr addrspace(4) %arg2, !tbaa !3
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150
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325 %i.i = extractelement <2 x i32> %arg7, i32 0
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326 %j.i = extractelement <2 x i32> %arg7, i32 1
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327 %i.f.i = bitcast i32 %i.i to float
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328 %j.f.i = bitcast i32 %j.i to float
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329 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0
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330 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0
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331 %i.i1 = extractelement <2 x i32> %arg7, i32 0
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332 %j.i2 = extractelement <2 x i32> %arg7, i32 1
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333 %i.f.i3 = bitcast i32 %i.i1 to float
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334 %j.f.i4 = bitcast i32 %j.i2 to float
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335 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #0
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336 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #0
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337 %tmp31 = bitcast float %tmp23 to i32
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338 %tmp36 = icmp ne i32 %tmp31, 0
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339 br i1 %tmp36, label %bb38, label %bb80
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340
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341 bb38: ; preds = %bb
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342 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32>
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343 %tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp56, <4 x i32> %tmp28, i1 0, i32 0, i32 0)
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344 br label %bb71
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345
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346 bb80: ; preds = %bb
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347 %tmp81 = bitcast float %p2.i to i32
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348 %tmp82 = bitcast float %p2.i6 to i32
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349 %tmp82.2 = add i32 %tmp82, 1
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350 %tmp83 = bitcast i32 %tmp81 to float
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351 %tmp84 = bitcast i32 %tmp82.2 to float
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352 %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32>
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353 %tmp3 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp83, float %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i1 0, i32 0, i32 0)
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354 br label %bb71
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355
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356 bb71: ; preds = %bb80, %bb38
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357 %tmp72 = phi <4 x float> [ %tmp2, %bb38 ], [ %tmp3, %bb80 ]
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358 %tmp88 = extractelement <4 x float> %tmp72, i32 0
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359 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0
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|
|
360 ret void
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|
|
361 }
|
|
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362
|
|
|
363 ; Check the resource descriptor is stored in an sgpr.
|
|
|
364 ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
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|
|
365 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
|
252
|
366 define amdgpu_ps void @mimg_srsrc_sgpr(ptr addrspace(4) inreg %arg) #0 {
|
|
150
|
367 bb:
|
|
|
368 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
|
|
252
|
369 %tmp7 = getelementptr [34 x <8 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid
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|
|
370 %tmp8 = load <8 x i32>, ptr addrspace(4) %tmp7, align 32, !tbaa !0
|
|
150
|
371 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> %tmp8, <4 x i32> undef, i1 0, i32 0, i32 0)
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372 %tmp10 = extractelement <4 x float> %tmp, i32 0
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|
|
373 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10)
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374 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
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|
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375 ret void
|
|
|
376 }
|
|
|
377
|
|
|
378 ; Check the sampler is stored in an sgpr.
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|
|
379 ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
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|
|
380 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
|
252
|
381 define amdgpu_ps void @mimg_ssamp_sgpr(ptr addrspace(4) inreg %arg) #0 {
|
|
150
|
382 bb:
|
|
|
383 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
|
|
252
|
384 %tmp7 = getelementptr [17 x <4 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid
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|
|
385 %tmp8 = load <4 x i32>, ptr addrspace(4) %tmp7, align 16, !tbaa !0
|
|
150
|
386 %tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> undef, <4 x i32> %tmp8, i1 0, i32 0, i32 0)
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|
|
387 %tmp10 = extractelement <4 x float> %tmp, i32 0
|
|
|
388 %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
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|
|
389 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
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|
|
390 ret void
|
|
|
391 }
|
|
|
392
|
|
|
393 declare float @llvm.fabs.f32(float) #1
|
|
|
394 declare float @llvm.amdgcn.rsq.f32(float) #1
|
|
|
395 declare float @llvm.exp2.f32(float) #1
|
|
|
396 declare float @llvm.pow.f32(float, float) #1
|
|
|
397 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
|
|
|
398 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
|
|
|
399 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
|
|
|
400 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
|
|
401 declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
|
|
|
402 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
|
|
|
403 declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
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|
|
404 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1
|
|
|
405
|
|
|
406 attributes #0 = { nounwind }
|
|
|
407 attributes #1 = { nounwind readnone }
|
|
|
408 attributes #2 = { nounwind readonly }
|
|
|
409
|
|
|
410 !0 = !{!1, !1, i64 0, i32 1}
|
|
|
411 !1 = !{!"const", !2}
|
|
|
412 !2 = !{!"tbaa root"}
|
|
|
413 !3 = !{!1, !1, i64 0}
|
