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1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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2 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
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3
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4 --- |
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5 define amdgpu_ps void @exit_to_exact() {
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6 ret void
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7 }
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8 ...
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9 ---
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10
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11 ---
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12 name: exit_to_exact
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13 tracksRegLiveness: true
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14 registers:
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15 - { id: 0, class: sgpr_32, preferred-register: '' }
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16 - { id: 1, class: vreg_64, preferred-register: '' }
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17 - { id: 2, class: sgpr_256, preferred-register: '' }
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18 - { id: 3, class: sgpr_128, preferred-register: '' }
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19 - { id: 4, class: vreg_96, preferred-register: '' }
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20 - { id: 5, class: vreg_64, preferred-register: '' }
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21 - { id: 6, class: vgpr_32, preferred-register: '' }
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22 liveins:
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23 - { reg: '$sgpr0', virtual-reg: '%0' }
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24 body: |
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25 ; CHECK-LABEL: name: exit_to_exact
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26 ; CHECK: bb.0:
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27 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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28 ; CHECK-NEXT: liveins: $sgpr0, $vgpr0_vgpr1
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29 ; CHECK-NEXT: {{ $}}
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30 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $exec_lo
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31 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
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32 ; CHECK-NEXT: $exec_lo = S_WQM_B32 $exec_lo, implicit-def $scc
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33 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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34 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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35 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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36 ; CHECK-NEXT: S_CMP_EQ_U32 [[COPY1]], 0, implicit-def $scc
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37 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec
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38 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MUL_F32_e64 0, [[COPY2]].sub0, 0, [[COPY2]].sub1, 0, 0, implicit $mode, implicit $exec
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39 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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40 ; CHECK-NEXT: $exec_lo = S_AND_B32 $exec_lo, [[COPY]], implicit-def $scc
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41 ; CHECK-NEXT: $scc = COPY [[COPY3]]
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42 ; CHECK-NEXT: [[IMAGE_SAMPLE_V3_V2_gfx10_:%[0-9]+]]:vreg_96 = IMAGE_SAMPLE_V3_V2_gfx10 %5, [[DEF]], [[DEF1]], 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
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43 ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc
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44 ; CHECK-NEXT: S_BRANCH %bb.1
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45 ; CHECK-NEXT: {{ $}}
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46 ; CHECK-NEXT: bb.1:
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47 ; CHECK-NEXT: successors: %bb.2(0x80000000)
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48 ; CHECK-NEXT: {{ $}}
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49 ; CHECK-NEXT: {{ $}}
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50 ; CHECK-NEXT: bb.2:
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51 ; CHECK-NEXT: [[V_SUB_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SUB_F32_e64 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, 0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, 0, 0, implicit $mode, implicit $exec
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52 ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET_exact [[V_SUB_F32_e64_]], [[DEF1]], [[COPY1]], 4, 0, 0, implicit $exec
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53 ; CHECK-NEXT: EXP 0, [[V_SUB_F32_e64_]], [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub0, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub1, [[IMAGE_SAMPLE_V3_V2_gfx10_]].sub2, 0, 0, 0, implicit $exec
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54 ; CHECK-NEXT: S_ENDPGM 0
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55 bb.0:
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56 liveins: $sgpr0, $vgpr0_vgpr1
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57
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58 %0 = COPY $sgpr0
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59 %1 = COPY $vgpr0_vgpr1
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60 %2 = IMPLICIT_DEF
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61 %3 = IMPLICIT_DEF
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62
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63 S_CMP_EQ_U32 %0, 0, implicit-def $scc
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64 undef %5.sub0 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec
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65 %5.sub1 = V_MUL_F32_e64 0, %1.sub0, 0, %1.sub1, 0, 0, implicit $mode, implicit $exec
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66 %4 = IMAGE_SAMPLE_V3_V2_gfx10 %5, %2, %3, 7, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s96), align 16, addrspace 8)
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67 S_CBRANCH_SCC1 %bb.2, implicit killed $scc
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68 S_BRANCH %bb.1
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69
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70 bb.1:
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71
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72 bb.2:
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73 %6 = nofpexcept V_SUB_F32_e64 0, %4.sub0, 0, %4.sub1, 0, 0, implicit $mode, implicit $exec
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74 BUFFER_STORE_DWORD_OFFSET_exact %6, %3, %0, 4, 0, 0, implicit $exec
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75 EXP 0, %6, %4.sub0, %4.sub1, %4.sub2, 0, 0, 0, implicit $exec
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76 S_ENDPGM 0
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77
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78 ...
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