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annotate polly/test/ScheduleOptimizer/vivid-vbi-gen-vivid_vbi_gen_sliced-before-llvmreduced.ll @ 252:1f2b6ac9f198 llvm-original

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LLVM16-1
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Fri, 18 Aug 2023 09:04:13 +0900
parents c4bab56944e8
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1 ; RUN: opt %loadPolly -polly-vectorizer=stripmine -polly-isl-arg=--no-schedule-serialize-sccs -polly-tiling=0 -polly-print-opt-isl -disable-output < %s | FileCheck %s
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2
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3 ; isl_schedule_node_band_sink may sink into multiple children.
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4 ; https://llvm.org/PR52637
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5
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6 %struct.v4l2_sliced_vbi_data = type { [48 x i8] }
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7
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8 define void @vivid_vbi_gen_sliced() {
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9 entry:
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10 br label %for.body
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11
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12 for.body: ; preds = %vivid_vbi_gen_teletext.exit, %entry
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13 %i.015 = phi i32 [ 0, %entry ], [ %inc, %vivid_vbi_gen_teletext.exit ]
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1f2b6ac9f198 LLVM16-1
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14 %data0.014 = phi ptr [ null, %entry ], [ %incdec.ptr, %vivid_vbi_gen_teletext.exit ]
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15 %arrayidx.i = getelementptr inbounds %struct.v4l2_sliced_vbi_data, ptr %data0.014, i32 0, i32 0, i32 6
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16 %0 = load i8, ptr %arrayidx.i, align 1
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17 store i8 %0, ptr %data0.014, align 1
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18 br label %for.body.for.body_crit_edge.i
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19
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20 for.body.for.body_crit_edge.i: ; preds = %for.body.for.body_crit_edge.i, %for.body
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21 %inc10.i13 = phi i32 [ 1, %for.body ], [ %inc10.i, %for.body.for.body_crit_edge.i ]
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22 %arrayidx2.phi.trans.insert.i = getelementptr inbounds %struct.v4l2_sliced_vbi_data, ptr %data0.014, i32 0, i32 0, i32 %inc10.i13
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23 store i8 0, ptr %arrayidx2.phi.trans.insert.i, align 1
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24 %inc10.i = add nuw nsw i32 %inc10.i13, 1
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25 %exitcond.not.i = icmp eq i32 %inc10.i13, 42
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26 br i1 %exitcond.not.i, label %vivid_vbi_gen_teletext.exit, label %for.body.for.body_crit_edge.i
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28 vivid_vbi_gen_teletext.exit: ; preds = %for.body.for.body_crit_edge.i
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29 %incdec.ptr = getelementptr inbounds %struct.v4l2_sliced_vbi_data, ptr %data0.014, i32 1
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30 %inc = add nuw nsw i32 %i.015, 1
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31 %exitcond.not = icmp eq i32 %i.015, 1
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32 br i1 %exitcond.not, label %for.end, label %for.body
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33
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34 for.end: ; preds = %vivid_vbi_gen_teletext.exit
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35 ret void
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36 }
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39 ; CHECK: schedule:
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40 ; CHECK: schedule:
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41 ; CHECK: mark: "SIMD"
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42 ; CHECK: schedule:
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43 ; CHECK: mark: "SIMD"
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44 ; CHECK: schedule: