|
236
|
1 ; RUN: opt %loadPolly -polly-print-scops -disable-output < %s | FileCheck %s
|
|
|
2 ; RUN: opt %loadPolly -polly-print-ast -disable-output < %s | FileCheck %s --check-prefix=AST
|
|
150
|
3 ;
|
|
|
4 ; void f(int *A, int N) {
|
|
|
5 ; for (int i = 0; i < N; i++) {
|
|
|
6 ; switch (i) {
|
|
|
7 ; case 0:
|
|
|
8 ; A[i] += 1;
|
|
|
9 ; break;
|
|
|
10 ; case 1:
|
|
|
11 ; A[i] += 2;
|
|
|
12 ; break;
|
|
|
13 ; case 2:
|
|
|
14 ; A[i] += 3;
|
|
|
15 ; break;
|
|
|
16 ; case 3:
|
|
|
17 ; A[i] += 4;
|
|
|
18 ; break;
|
|
|
19 ; default:;
|
|
|
20 ; }
|
|
|
21 ; }
|
|
|
22 ; }
|
|
|
23
|
|
|
24 ; CHECK: Statements {
|
|
|
25 ; CHECK-NEXT: Stmt_sw_bb
|
|
|
26 ; CHECK-NEXT: Domain :=
|
|
|
27 ; CHECK-NEXT: [N] -> { Stmt_sw_bb[0] : N > 0 };
|
|
|
28 ; CHECK-NEXT: Schedule :=
|
|
|
29 ; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] -> [0, 3] };
|
|
|
30 ; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
31 ; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] -> MemRef_A[0] };
|
|
|
32 ; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
33 ; CHECK-NEXT: [N] -> { Stmt_sw_bb[i0] -> MemRef_A[0] };
|
|
|
34 ; CHECK-NEXT: Stmt_sw_bb_1
|
|
|
35 ; CHECK-NEXT: Domain :=
|
|
|
36 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[1] : N >= 2 };
|
|
|
37 ; CHECK-NEXT: Schedule :=
|
|
|
38 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] -> [1, 2] };
|
|
|
39 ; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
40 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] -> MemRef_A[1] };
|
|
|
41 ; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
42 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_1[i0] -> MemRef_A[1] };
|
|
|
43 ; CHECK-NEXT: Stmt_sw_bb_5
|
|
|
44 ; CHECK-NEXT: Domain :=
|
|
|
45 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[2] : N >= 3 };
|
|
|
46 ; CHECK-NEXT: Schedule :=
|
|
|
47 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] -> [2, 1] };
|
|
|
48 ; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
49 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] -> MemRef_A[2] };
|
|
|
50 ; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
51 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_5[i0] -> MemRef_A[2] };
|
|
|
52 ; CHECK-NEXT: Stmt_sw_bb_9
|
|
|
53 ; CHECK-NEXT: Domain :=
|
|
|
54 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[3] : N >= 4 };
|
|
|
55 ; CHECK-NEXT: Schedule :=
|
|
|
56 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] -> [3, 0] };
|
|
|
57 ; CHECK-NEXT: ReadAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
58 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] -> MemRef_A[3] };
|
|
|
59 ; CHECK-NEXT: MustWriteAccess := [Reduction Type: +] [Scalar: 0]
|
|
|
60 ; CHECK-NEXT: [N] -> { Stmt_sw_bb_9[i0] -> MemRef_A[3] };
|
|
|
61 ; CHECK-NEXT: }
|
|
|
62
|
|
|
63 ; AST: if (1)
|
|
|
64 ;
|
|
|
65 ; AST: if (N >= 1) {
|
|
|
66 ; AST-NEXT: Stmt_sw_bb(0);
|
|
|
67 ; AST-NEXT: if (N >= 2) {
|
|
|
68 ; AST-NEXT: Stmt_sw_bb_1(1);
|
|
|
69 ; AST-NEXT: if (N >= 3) {
|
|
|
70 ; AST-NEXT: Stmt_sw_bb_5(2);
|
|
|
71 ; AST-NEXT: if (N >= 4)
|
|
|
72 ; AST-NEXT: Stmt_sw_bb_9(3);
|
|
|
73 ; AST-NEXT: }
|
|
|
74 ; AST-NEXT: }
|
|
|
75 ; AST-NEXT: }
|
|
|
76 ;
|
|
|
77 ; AST: else
|
|
|
78 ; AST-NEXT: { /* original code */ }
|
|
|
79
|
|
|
80 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
|
|
81
|
|
252
|
82 define void @f(ptr %A, i32 %N) {
|
|
150
|
83 entry:
|
|
|
84 %tmp = sext i32 %N to i64
|
|
|
85 br label %for.cond
|
|
|
86
|
|
|
87 for.cond: ; preds = %for.inc, %entry
|
|
|
88 %indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
|
|
|
89 %cmp = icmp slt i64 %indvars.iv, %tmp
|
|
|
90 br i1 %cmp, label %for.body, label %for.end
|
|
|
91
|
|
|
92 for.body: ; preds = %for.cond
|
|
|
93 %tmp1 = trunc i64 %indvars.iv to i32
|
|
|
94 switch i32 %tmp1, label %sw.default [
|
|
|
95 i32 0, label %sw.bb
|
|
|
96 i32 1, label %sw.bb.1
|
|
|
97 i32 2, label %sw.bb.5
|
|
|
98 i32 3, label %sw.bb.9
|
|
|
99 ]
|
|
|
100
|
|
|
101 sw.bb: ; preds = %for.body
|
|
252
|
102 %arrayidx = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
|
|
|
103 %tmp2 = load i32, ptr %arrayidx, align 4
|
|
150
|
104 %add = add nsw i32 %tmp2, 1
|
|
252
|
105 store i32 %add, ptr %arrayidx, align 4
|
|
150
|
106 br label %sw.epilog
|
|
|
107
|
|
|
108 sw.bb.1: ; preds = %for.body
|
|
252
|
109 %arrayidx3 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
|
|
|
110 %tmp3 = load i32, ptr %arrayidx3, align 4
|
|
150
|
111 %add4 = add nsw i32 %tmp3, 2
|
|
252
|
112 store i32 %add4, ptr %arrayidx3, align 4
|
|
150
|
113 br label %sw.epilog
|
|
|
114
|
|
|
115 sw.bb.5: ; preds = %for.body
|
|
252
|
116 %arrayidx7 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
|
|
|
117 %tmp4 = load i32, ptr %arrayidx7, align 4
|
|
150
|
118 %add8 = add nsw i32 %tmp4, 3
|
|
252
|
119 store i32 %add8, ptr %arrayidx7, align 4
|
|
150
|
120 br label %sw.epilog
|
|
|
121
|
|
|
122 sw.bb.9: ; preds = %for.body
|
|
252
|
123 %arrayidx11 = getelementptr inbounds i32, ptr %A, i64 %indvars.iv
|
|
|
124 %tmp5 = load i32, ptr %arrayidx11, align 4
|
|
150
|
125 %add12 = add nsw i32 %tmp5, 4
|
|
252
|
126 store i32 %add12, ptr %arrayidx11, align 4
|
|
150
|
127 br label %sw.epilog
|
|
|
128
|
|
|
129 sw.default: ; preds = %for.body
|
|
|
130 br label %sw.epilog
|
|
|
131
|
|
|
132 sw.epilog: ; preds = %sw.default, %sw.bb.9, %sw.bb.5, %sw.bb.1, %sw.bb
|
|
|
133 br label %for.inc
|
|
|
134
|
|
|
135 for.inc: ; preds = %sw.epilog
|
|
|
136 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
|
|
|
137 br label %for.cond
|
|
|
138
|
|
|
139 for.end: ; preds = %for.cond
|
|
|
140 ret void
|
|
|
141 }
|
