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1 //===--- PPC.cpp - Implement PPC target feature support -------------------===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file implements PPC TargetInfo objects.
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10 //
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11 //===----------------------------------------------------------------------===//
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12
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13 #include "PPC.h"
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14 #include "clang/Basic/Diagnostic.h"
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15 #include "clang/Basic/MacroBuilder.h"
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16 #include "clang/Basic/TargetBuiltins.h"
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17
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18 using namespace clang;
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19 using namespace clang::targets;
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20
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21 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
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22 #define BUILTIN(ID, TYPE, ATTRS) \
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23 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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24 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
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25 {#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
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26 #include "clang/Basic/BuiltinsPPC.def"
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27 };
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28
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29 /// handleTargetFeatures - Perform initialization based on the user
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30 /// configured set of features.
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31 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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32 DiagnosticsEngine &Diags) {
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33 FloatABI = HardFloat;
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34 for (const auto &Feature : Features) {
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35 if (Feature == "+altivec") {
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36 HasAltivec = true;
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37 } else if (Feature == "+vsx") {
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38 HasVSX = true;
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39 } else if (Feature == "+bpermd") {
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40 HasBPERMD = true;
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41 } else if (Feature == "+extdiv") {
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42 HasExtDiv = true;
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43 } else if (Feature == "+power8-vector") {
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44 HasP8Vector = true;
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45 } else if (Feature == "+crypto") {
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46 HasP8Crypto = true;
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47 } else if (Feature == "+direct-move") {
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48 HasDirectMove = true;
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49 } else if (Feature == "+htm") {
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50 HasHTM = true;
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51 } else if (Feature == "+float128") {
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52 HasFloat128 = true;
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53 } else if (Feature == "+power9-vector") {
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54 HasP9Vector = true;
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207
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55 } else if (Feature == "+power10-vector") {
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56 HasP10Vector = true;
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57 } else if (Feature == "+pcrelative-memops") {
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58 HasPCRelativeMemops = true;
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59 } else if (Feature == "+prefix-instrs") {
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60 HasPrefixInstrs = true;
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61 } else if (Feature == "+spe" || Feature == "+efpu2") {
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62 HasStrictFP = false;
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150
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63 HasSPE = true;
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64 LongDoubleWidth = LongDoubleAlign = 64;
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65 LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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66 } else if (Feature == "-hard-float") {
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67 FloatABI = SoftFloat;
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207
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68 } else if (Feature == "+paired-vector-memops") {
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69 PairedVectorMemops = true;
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70 } else if (Feature == "+mma") {
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71 HasMMA = true;
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72 } else if (Feature == "+rop-protect") {
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73 HasROPProtect = true;
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74 } else if (Feature == "+privileged") {
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75 HasPrivileged = true;
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150
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76 }
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77 // TODO: Finish this list and add an assert that we've handled them
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78 // all.
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79 }
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80
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81 return true;
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82 }
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83
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84 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
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85 /// #defines that are not tied to a specific subtarget.
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86 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
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87 MacroBuilder &Builder) const {
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207
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88
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89 defineXLCompatMacros(Builder);
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90
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150
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91 // Target identification.
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92 Builder.defineMacro("__ppc__");
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93 Builder.defineMacro("__PPC__");
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94 Builder.defineMacro("_ARCH_PPC");
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95 Builder.defineMacro("__powerpc__");
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96 Builder.defineMacro("__POWERPC__");
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97 if (PointerWidth == 64) {
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98 Builder.defineMacro("_ARCH_PPC64");
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99 Builder.defineMacro("__powerpc64__");
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100 Builder.defineMacro("__ppc64__");
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101 Builder.defineMacro("__PPC64__");
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102 }
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103
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104 // Target properties.
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207
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105 if (getTriple().getArch() == llvm::Triple::ppc64le ||
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106 getTriple().getArch() == llvm::Triple::ppcle) {
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150
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107 Builder.defineMacro("_LITTLE_ENDIAN");
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108 } else {
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109 if (!getTriple().isOSNetBSD() &&
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110 !getTriple().isOSOpenBSD())
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111 Builder.defineMacro("_BIG_ENDIAN");
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112 }
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113
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114 // ABI options.
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207
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115 if (ABI == "elfv1")
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150
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116 Builder.defineMacro("_CALL_ELF", "1");
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117 if (ABI == "elfv2")
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118 Builder.defineMacro("_CALL_ELF", "2");
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119
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120 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
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121 // our support post-dates this and it should work on all 64-bit ppc linux
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122 // platforms. It is guaranteed to work on all elfv2 platforms.
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123 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64)
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124 Builder.defineMacro("_CALL_LINUX", "1");
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125
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126 // Subtarget options.
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127 if (!getTriple().isOSAIX()){
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128 Builder.defineMacro("__NATURAL_ALIGNMENT__");
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129 }
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130 Builder.defineMacro("__REGISTER_PREFIX__", "");
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131
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132 // FIXME: Should be controlled by command line option.
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133 if (LongDoubleWidth == 128) {
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134 Builder.defineMacro("__LONG_DOUBLE_128__");
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135 Builder.defineMacro("__LONGDOUBLE128");
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207
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136 if (Opts.PPCIEEELongDouble)
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137 Builder.defineMacro("__LONG_DOUBLE_IEEE128__");
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138 else
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139 Builder.defineMacro("__LONG_DOUBLE_IBM128__");
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150
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140 }
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141
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142 // Define this for elfv2 (64-bit only) or 64-bit darwin.
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143 if (ABI == "elfv2" ||
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144 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64))
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145 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16");
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146
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147 if (ArchDefs & ArchDefineName)
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148 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
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149 if (ArchDefs & ArchDefinePpcgr)
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150 Builder.defineMacro("_ARCH_PPCGR");
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151 if (ArchDefs & ArchDefinePpcsq)
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152 Builder.defineMacro("_ARCH_PPCSQ");
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153 if (ArchDefs & ArchDefine440)
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154 Builder.defineMacro("_ARCH_440");
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155 if (ArchDefs & ArchDefine603)
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156 Builder.defineMacro("_ARCH_603");
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157 if (ArchDefs & ArchDefine604)
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158 Builder.defineMacro("_ARCH_604");
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159 if (ArchDefs & ArchDefinePwr4)
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160 Builder.defineMacro("_ARCH_PWR4");
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161 if (ArchDefs & ArchDefinePwr5)
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162 Builder.defineMacro("_ARCH_PWR5");
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163 if (ArchDefs & ArchDefinePwr5x)
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164 Builder.defineMacro("_ARCH_PWR5X");
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165 if (ArchDefs & ArchDefinePwr6)
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166 Builder.defineMacro("_ARCH_PWR6");
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167 if (ArchDefs & ArchDefinePwr6x)
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168 Builder.defineMacro("_ARCH_PWR6X");
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169 if (ArchDefs & ArchDefinePwr7)
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170 Builder.defineMacro("_ARCH_PWR7");
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171 if (ArchDefs & ArchDefinePwr8)
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172 Builder.defineMacro("_ARCH_PWR8");
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173 if (ArchDefs & ArchDefinePwr9)
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174 Builder.defineMacro("_ARCH_PWR9");
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207
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175 if (ArchDefs & ArchDefinePwr10)
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176 Builder.defineMacro("_ARCH_PWR10");
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150
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177 if (ArchDefs & ArchDefineA2)
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178 Builder.defineMacro("_ARCH_A2");
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179 if (ArchDefs & ArchDefineE500)
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180 Builder.defineMacro("__NO_LWSYNC__");
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181 if (ArchDefs & ArchDefineFuture)
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182 Builder.defineMacro("_ARCH_PWR_FUTURE");
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183
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184 if (HasAltivec) {
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185 Builder.defineMacro("__VEC__", "10206");
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186 Builder.defineMacro("__ALTIVEC__");
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187 }
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188 if (HasSPE) {
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189 Builder.defineMacro("__SPE__");
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190 Builder.defineMacro("__NO_FPRS__");
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191 }
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192 if (HasVSX)
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193 Builder.defineMacro("__VSX__");
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194 if (HasP8Vector)
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195 Builder.defineMacro("__POWER8_VECTOR__");
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196 if (HasP8Crypto)
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197 Builder.defineMacro("__CRYPTO__");
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198 if (HasHTM)
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199 Builder.defineMacro("__HTM__");
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200 if (HasFloat128)
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201 Builder.defineMacro("__FLOAT128__");
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202 if (HasP9Vector)
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203 Builder.defineMacro("__POWER9_VECTOR__");
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207
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204 if (HasMMA)
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205 Builder.defineMacro("__MMA__");
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206 if (HasROPProtect)
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207 Builder.defineMacro("__ROP_PROTECT__");
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208 if (HasPrivileged)
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209 Builder.defineMacro("__PRIVILEGED__");
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210 if (HasP10Vector)
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211 Builder.defineMacro("__POWER10_VECTOR__");
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212 if (HasPCRelativeMemops)
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213 Builder.defineMacro("__PCREL__");
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150
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214
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215 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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216 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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217 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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218 if (PointerWidth == 64)
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219 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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220
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221 // We have support for the bswap intrinsics so we can define this.
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222 Builder.defineMacro("__HAVE_BSWAP__", "1");
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223
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224 // FIXME: The following are not yet generated here by Clang, but are
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225 // generated by GCC:
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226 //
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227 // _SOFT_FLOAT_
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228 // __RECIP_PRECISION__
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229 // __APPLE_ALTIVEC__
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230 // __RECIP__
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231 // __RECIPF__
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232 // __RSQRTE__
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233 // __RSQRTEF__
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234 // _SOFT_DOUBLE_
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235 // __NO_LWSYNC__
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236 // __CMODEL_MEDIUM__
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237 // __CMODEL_LARGE__
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238 // _CALL_SYSV
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239 // _CALL_DARWIN
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240 }
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241
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242 // Handle explicit options being passed to the compiler here: if we've
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243 // explicitly turned off vsx and turned on any of:
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244 // - power8-vector
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245 // - direct-move
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246 // - float128
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247 // - power9-vector
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207
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248 // - paired-vector-memops
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249 // - mma
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250 // - power10-vector
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150
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251 // then go ahead and error since the customer has expressed an incompatible
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252 // set of options.
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253 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
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254 const std::vector<std::string> &FeaturesVec) {
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255
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173
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256 // vsx was not explicitly turned off.
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257 if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
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258 return true;
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150
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259
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173
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260 auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) {
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261 if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
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262 Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
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263 return true;
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150
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264 }
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173
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265 return false;
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266 };
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150
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267
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173
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268 bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
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269 Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
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270 Found |= FindVSXSubfeature("+float128", "-mfloat128");
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271 Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
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207
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272 Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
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273 Found |= FindVSXSubfeature("+mma", "-mmma");
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274 Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
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150
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275
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173
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276 // Return false if any vsx subfeatures was found.
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277 return !Found;
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150
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278 }
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279
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280 bool PPCTargetInfo::initFeatureMap(
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281 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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282 const std::vector<std::string> &FeaturesVec) const {
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283 Features["altivec"] = llvm::StringSwitch<bool>(CPU)
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284 .Case("7400", true)
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285 .Case("g4", true)
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286 .Case("7450", true)
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287 .Case("g4+", true)
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288 .Case("970", true)
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289 .Case("g5", true)
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290 .Case("pwr6", true)
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291 .Case("pwr7", true)
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292 .Case("pwr8", true)
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293 .Case("pwr9", true)
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294 .Case("ppc64", true)
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295 .Case("ppc64le", true)
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296 .Default(false);
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297
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298 Features["power9-vector"] = (CPU == "pwr9");
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299 Features["crypto"] = llvm::StringSwitch<bool>(CPU)
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300 .Case("ppc64le", true)
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301 .Case("pwr9", true)
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302 .Case("pwr8", true)
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303 .Default(false);
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304 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
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305 .Case("ppc64le", true)
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306 .Case("pwr9", true)
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307 .Case("pwr8", true)
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308 .Default(false);
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309 Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
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310 .Case("ppc64le", true)
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311 .Case("pwr9", true)
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312 .Case("pwr8", true)
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313 .Case("pwr7", true)
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314 .Default(false);
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315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
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316 .Case("ppc64le", true)
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317 .Case("pwr9", true)
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318 .Case("pwr8", true)
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319 .Case("pwr7", true)
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320 .Default(false);
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321 Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
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322 .Case("ppc64le", true)
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323 .Case("pwr9", true)
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324 .Case("pwr8", true)
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325 .Default(false);
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326 Features["vsx"] = llvm::StringSwitch<bool>(CPU)
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327 .Case("ppc64le", true)
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328 .Case("pwr9", true)
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329 .Case("pwr8", true)
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330 .Case("pwr7", true)
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331 .Default(false);
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332 Features["htm"] = llvm::StringSwitch<bool>(CPU)
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333 .Case("ppc64le", true)
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334 .Case("pwr9", true)
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335 .Case("pwr8", true)
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336 .Default(false);
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337
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207
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338 // ROP Protect is off by default.
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339 Features["rop-protect"] = false;
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340 // Privileged instructions are off by default.
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341 Features["privileged"] = false;
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342
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150
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343 Features["spe"] = llvm::StringSwitch<bool>(CPU)
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344 .Case("8548", true)
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345 .Case("e500", true)
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346 .Default(false);
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347
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207
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348 // Power10 includes all the same features as Power9 plus any features specific
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349 // to the Power10 core.
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350 if (CPU == "pwr10" || CPU == "power10") {
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351 initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
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352 addP10SpecificFeatures(Features);
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353 }
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354
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355 // Future CPU should include all of the features of Power 10 as well as any
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150
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356 // additional features (yet to be determined) specific to it.
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357 if (CPU == "future") {
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207
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358 initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
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150
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359 addFutureSpecificFeatures(Features);
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360 }
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361
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362 if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
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363 return false;
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364
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365 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
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366 llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
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367 // We have __float128 on PPC but not power 9 and above.
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368 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
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369 return false;
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370 }
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371
|
|
207
|
372 if (!(ArchDefs & ArchDefinePwr10) &&
|
|
|
373 llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) {
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|
|
374 // We have MMA on PPC but not power 10 and above.
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|
375 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
|
|
|
376 return false;
|
|
|
377 }
|
|
|
378
|
|
|
379 if (!(ArchDefs & ArchDefinePwr8) &&
|
|
|
380 llvm::find(FeaturesVec, "+rop-protect") != FeaturesVec.end()) {
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|
|
381 // We can turn on ROP Protect on Power 8 and above.
|
|
|
382 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mrop-protect" << CPU;
|
|
|
383 return false;
|
|
|
384 }
|
|
|
385
|
|
|
386 if (!(ArchDefs & ArchDefinePwr8) &&
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|
387 llvm::find(FeaturesVec, "+privileged") != FeaturesVec.end()) {
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|
388 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mprivileged" << CPU;
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|
|
389 return false;
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|
|
390 }
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|
|
391
|
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150
|
392 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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|
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393 }
|
|
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394
|
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207
|
395 // Add any Power10 specific features.
|
|
|
396 void PPCTargetInfo::addP10SpecificFeatures(
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|
397 llvm::StringMap<bool> &Features) const {
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|
|
398 Features["htm"] = false; // HTM was removed for P10.
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|
399 Features["paired-vector-memops"] = true;
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|
400 Features["mma"] = true;
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|
401 Features["power10-vector"] = true;
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402 Features["pcrelative-memops"] = true;
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|
403 Features["prefix-instrs"] = true;
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|
|
404 return;
|
|
|
405 }
|
|
|
406
|
|
150
|
407 // Add features specific to the "Future" CPU.
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|
|
408 void PPCTargetInfo::addFutureSpecificFeatures(
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|
|
409 llvm::StringMap<bool> &Features) const {
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|
|
410 return;
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|
|
411 }
|
|
|
412
|
|
|
413 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
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|
|
414 return llvm::StringSwitch<bool>(Feature)
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415 .Case("powerpc", true)
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416 .Case("altivec", HasAltivec)
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|
417 .Case("vsx", HasVSX)
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|
|
418 .Case("power8-vector", HasP8Vector)
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419 .Case("crypto", HasP8Crypto)
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420 .Case("direct-move", HasDirectMove)
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|
421 .Case("htm", HasHTM)
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|
422 .Case("bpermd", HasBPERMD)
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|
|
423 .Case("extdiv", HasExtDiv)
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|
|
424 .Case("float128", HasFloat128)
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|
|
425 .Case("power9-vector", HasP9Vector)
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207
|
426 .Case("paired-vector-memops", PairedVectorMemops)
|
|
|
427 .Case("power10-vector", HasP10Vector)
|
|
|
428 .Case("pcrelative-memops", HasPCRelativeMemops)
|
|
|
429 .Case("prefix-instrs", HasPrefixInstrs)
|
|
150
|
430 .Case("spe", HasSPE)
|
|
207
|
431 .Case("mma", HasMMA)
|
|
|
432 .Case("rop-protect", HasROPProtect)
|
|
|
433 .Case("privileged", HasPrivileged)
|
|
150
|
434 .Default(false);
|
|
|
435 }
|
|
|
436
|
|
|
437 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
|
|
|
438 StringRef Name, bool Enabled) const {
|
|
|
439 if (Enabled) {
|
|
207
|
440 if (Name == "efpu2")
|
|
|
441 Features["spe"] = true;
|
|
150
|
442 // If we're enabling any of the vsx based features then enable vsx and
|
|
|
443 // altivec. We'll diagnose any problems later.
|
|
|
444 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name)
|
|
|
445 .Case("vsx", true)
|
|
|
446 .Case("direct-move", true)
|
|
|
447 .Case("power8-vector", true)
|
|
|
448 .Case("power9-vector", true)
|
|
207
|
449 .Case("paired-vector-memops", true)
|
|
|
450 .Case("power10-vector", true)
|
|
150
|
451 .Case("float128", true)
|
|
207
|
452 .Case("mma", true)
|
|
150
|
453 .Default(false);
|
|
|
454 if (FeatureHasVSX)
|
|
|
455 Features["vsx"] = Features["altivec"] = true;
|
|
|
456 if (Name == "power9-vector")
|
|
|
457 Features["power8-vector"] = true;
|
|
207
|
458 else if (Name == "power10-vector")
|
|
|
459 Features["power8-vector"] = Features["power9-vector"] = true;
|
|
|
460 if (Name == "pcrel")
|
|
|
461 Features["pcrelative-memops"] = true;
|
|
|
462 else if (Name == "prefixed")
|
|
|
463 Features["prefix-instrs"] = true;
|
|
|
464 else
|
|
|
465 Features[Name] = true;
|
|
150
|
466 } else {
|
|
207
|
467 if (Name == "spe")
|
|
|
468 Features["efpu2"] = false;
|
|
150
|
469 // If we're disabling altivec or vsx go ahead and disable all of the vsx
|
|
|
470 // features.
|
|
|
471 if ((Name == "altivec") || (Name == "vsx"))
|
|
|
472 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
|
|
207
|
473 Features["float128"] = Features["power9-vector"] =
|
|
|
474 Features["paired-vector-memops"] = Features["mma"] =
|
|
|
475 Features["power10-vector"] = false;
|
|
150
|
476 if (Name == "power8-vector")
|
|
207
|
477 Features["power9-vector"] = Features["paired-vector-memops"] =
|
|
|
478 Features["mma"] = Features["power10-vector"] = false;
|
|
|
479 else if (Name == "power9-vector")
|
|
|
480 Features["paired-vector-memops"] = Features["mma"] =
|
|
|
481 Features["power10-vector"] = false;
|
|
|
482 if (Name == "pcrel")
|
|
|
483 Features["pcrelative-memops"] = false;
|
|
|
484 else if (Name == "prefixed")
|
|
|
485 Features["prefix-instrs"] = false;
|
|
|
486 else
|
|
|
487 Features[Name] = false;
|
|
150
|
488 }
|
|
|
489 }
|
|
|
490
|
|
|
491 const char *const PPCTargetInfo::GCCRegNames[] = {
|
|
|
492 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
|
|
|
493 "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
|
|
|
494 "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26",
|
|
|
495 "r27", "r28", "r29", "r30", "r31", "f0", "f1", "f2", "f3",
|
|
|
496 "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12",
|
|
|
497 "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
|
|
|
498 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
|
|
|
499 "f31", "mq", "lr", "ctr", "ap", "cr0", "cr1", "cr2", "cr3",
|
|
|
500 "cr4", "cr5", "cr6", "cr7", "xer", "v0", "v1", "v2", "v3",
|
|
|
501 "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12",
|
|
|
502 "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
|
|
|
503 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30",
|
|
|
504 "v31", "vrsave", "vscr", "spe_acc", "spefscr", "sfp"
|
|
|
505 };
|
|
|
506
|
|
|
507 ArrayRef<const char *> PPCTargetInfo::getGCCRegNames() const {
|
|
|
508 return llvm::makeArrayRef(GCCRegNames);
|
|
|
509 }
|
|
|
510
|
|
|
511 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
|
|
|
512 // While some of these aliases do map to different registers
|
|
|
513 // they still share the same register name.
|
|
|
514 {{"0"}, "r0"}, {{"1"}, "r1"}, {{"2"}, "r2"}, {{"3"}, "r3"},
|
|
|
515 {{"4"}, "r4"}, {{"5"}, "r5"}, {{"6"}, "r6"}, {{"7"}, "r7"},
|
|
|
516 {{"8"}, "r8"}, {{"9"}, "r9"}, {{"10"}, "r10"}, {{"11"}, "r11"},
|
|
|
517 {{"12"}, "r12"}, {{"13"}, "r13"}, {{"14"}, "r14"}, {{"15"}, "r15"},
|
|
|
518 {{"16"}, "r16"}, {{"17"}, "r17"}, {{"18"}, "r18"}, {{"19"}, "r19"},
|
|
|
519 {{"20"}, "r20"}, {{"21"}, "r21"}, {{"22"}, "r22"}, {{"23"}, "r23"},
|
|
|
520 {{"24"}, "r24"}, {{"25"}, "r25"}, {{"26"}, "r26"}, {{"27"}, "r27"},
|
|
|
521 {{"28"}, "r28"}, {{"29"}, "r29"}, {{"30"}, "r30"}, {{"31"}, "r31"},
|
|
|
522 {{"fr0"}, "f0"}, {{"fr1"}, "f1"}, {{"fr2"}, "f2"}, {{"fr3"}, "f3"},
|
|
|
523 {{"fr4"}, "f4"}, {{"fr5"}, "f5"}, {{"fr6"}, "f6"}, {{"fr7"}, "f7"},
|
|
|
524 {{"fr8"}, "f8"}, {{"fr9"}, "f9"}, {{"fr10"}, "f10"}, {{"fr11"}, "f11"},
|
|
|
525 {{"fr12"}, "f12"}, {{"fr13"}, "f13"}, {{"fr14"}, "f14"}, {{"fr15"}, "f15"},
|
|
|
526 {{"fr16"}, "f16"}, {{"fr17"}, "f17"}, {{"fr18"}, "f18"}, {{"fr19"}, "f19"},
|
|
|
527 {{"fr20"}, "f20"}, {{"fr21"}, "f21"}, {{"fr22"}, "f22"}, {{"fr23"}, "f23"},
|
|
|
528 {{"fr24"}, "f24"}, {{"fr25"}, "f25"}, {{"fr26"}, "f26"}, {{"fr27"}, "f27"},
|
|
|
529 {{"fr28"}, "f28"}, {{"fr29"}, "f29"}, {{"fr30"}, "f30"}, {{"fr31"}, "f31"},
|
|
|
530 {{"cc"}, "cr0"},
|
|
|
531 };
|
|
|
532
|
|
|
533 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
|
|
|
534 return llvm::makeArrayRef(GCCRegAliases);
|
|
|
535 }
|
|
|
536
|
|
|
537 // PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
|
|
|
538 // vs0 ~ vs31 is mapping to 32 - 63,
|
|
|
539 // vs32 ~ vs63 is mapping to 77 - 108.
|
|
|
540 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
|
|
|
541 // Table of additional register names to use in user input.
|
|
|
542 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
|
|
|
543 {{"vs4"}, 36}, {{"vs5"}, 37}, {{"vs6"}, 38}, {{"vs7"}, 39},
|
|
|
544 {{"vs8"}, 40}, {{"vs9"}, 41}, {{"vs10"}, 42}, {{"vs11"}, 43},
|
|
|
545 {{"vs12"}, 44}, {{"vs13"}, 45}, {{"vs14"}, 46}, {{"vs15"}, 47},
|
|
|
546 {{"vs16"}, 48}, {{"vs17"}, 49}, {{"vs18"}, 50}, {{"vs19"}, 51},
|
|
|
547 {{"vs20"}, 52}, {{"vs21"}, 53}, {{"vs22"}, 54}, {{"vs23"}, 55},
|
|
|
548 {{"vs24"}, 56}, {{"vs25"}, 57}, {{"vs26"}, 58}, {{"vs27"}, 59},
|
|
|
549 {{"vs28"}, 60}, {{"vs29"}, 61}, {{"vs30"}, 62}, {{"vs31"}, 63},
|
|
|
550 {{"vs32"}, 77}, {{"vs33"}, 78}, {{"vs34"}, 79}, {{"vs35"}, 80},
|
|
|
551 {{"vs36"}, 81}, {{"vs37"}, 82}, {{"vs38"}, 83}, {{"vs39"}, 84},
|
|
|
552 {{"vs40"}, 85}, {{"vs41"}, 86}, {{"vs42"}, 87}, {{"vs43"}, 88},
|
|
|
553 {{"vs44"}, 89}, {{"vs45"}, 90}, {{"vs46"}, 91}, {{"vs47"}, 92},
|
|
|
554 {{"vs48"}, 93}, {{"vs49"}, 94}, {{"vs50"}, 95}, {{"vs51"}, 96},
|
|
|
555 {{"vs52"}, 97}, {{"vs53"}, 98}, {{"vs54"}, 99}, {{"vs55"}, 100},
|
|
|
556 {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
|
|
|
557 {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
|
|
|
558 };
|
|
|
559
|
|
|
560 ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
|
|
|
561 if (ABI == "elfv2")
|
|
|
562 return llvm::makeArrayRef(GCCAddlRegNames);
|
|
|
563 else
|
|
|
564 return TargetInfo::getGCCAddlRegNames();
|
|
|
565 }
|
|
|
566
|
|
|
567 static constexpr llvm::StringLiteral ValidCPUNames[] = {
|
|
207
|
568 {"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
|
|
|
569 {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
|
|
|
570 {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
|
|
|
571 {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
|
|
|
572 {"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"},
|
|
|
573 {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"},
|
|
|
574 {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"},
|
|
|
575 {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
|
|
|
576 {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
|
|
|
577 {"powerpc"}, {"ppc"}, {"ppc32"}, {"powerpc64"}, {"ppc64"},
|
|
|
578 {"powerpc64le"}, {"ppc64le"}, {"future"}};
|
|
150
|
579
|
|
|
580 bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
|
|
|
581 return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
|
|
|
582 }
|
|
|
583
|
|
|
584 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
|
|
|
585 Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
|
|
|
586 }
|
|
|
587
|
|
|
588 void PPCTargetInfo::adjust(LangOptions &Opts) {
|
|
|
589 if (HasAltivec)
|
|
|
590 Opts.AltiVec = 1;
|
|
|
591 TargetInfo::adjust(Opts);
|
|
|
592 if (LongDoubleFormat != &llvm::APFloat::IEEEdouble())
|
|
|
593 LongDoubleFormat = Opts.PPCIEEELongDouble
|
|
|
594 ? &llvm::APFloat::IEEEquad()
|
|
|
595 : &llvm::APFloat::PPCDoubleDouble();
|
|
207
|
596 Opts.IEEE128 = 1;
|
|
150
|
597 }
|
|
|
598
|
|
|
599 ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const {
|
|
|
600 return llvm::makeArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin -
|
|
|
601 Builtin::FirstTSBuiltin);
|
|
|
602 }
|
