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207
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1 // RUN: %clang_cc1 \
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2 // RUN: -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
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3 // RUN: -disable-O0-optnone -emit-llvm -o - %s \
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4 // RUN: | opt -S -mem2reg -instcombine \
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5 // RUN: | FileCheck --check-prefixes=CHECK,CHECK-A64 %s
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6 // RUN: %clang_cc1 \
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7 // RUN: -triple armv8.6a-arm-none-eabi -target-feature +neon \
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8 // RUN: -target-feature +bf16 -mfloat-abi hard \
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9 // RUN: -disable-O0-optnone -emit-llvm -o - %s \
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10 // RUN: | opt -S -mem2reg -instcombine \
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11 // RUN: | FileCheck --check-prefixes=CHECK,CHECK-A32-HARDFP %s
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12 // RUN: %clang_cc1 \
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13 // RUN: -triple armv8.6a-arm-none-eabi -target-feature +neon \
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14 // RUN: -target-feature +bf16 -mfloat-abi softfp \
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15 // RUN: -disable-O0-optnone -emit-llvm -o - %s \
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16 // RUN: | opt -S -mem2reg -instcombine \
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17 // RUN: | FileCheck --check-prefixes=CHECK,CHECK-A32-SOFTFP %s
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18
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19 #include <arm_neon.h>
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20
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21 // CHECK-LABEL: test_vcvt_f32_bf16
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22 // CHECK: %[[EXT:.*]] = zext <4 x i16> %{{.*}} to <4 x i32>
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23 // CHECK: shl nuw <4 x i32> %[[EXT]], <i32 16, i32 16, i32 16, i32 16>
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24 float32x4_t test_vcvt_f32_bf16(bfloat16x4_t a) {
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25 return vcvt_f32_bf16(a);
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26 }
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27
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28 // CHECK-LABEL: test_vcvtq_low_f32_bf16
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29 // CHECK: shufflevector <8 x bfloat> %{{.*}}, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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30 // CHECK: %[[EXT:.*]] = zext <4 x i16> %{{.*}} to <4 x i32>
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31 // CHECK: shl nuw <4 x i32> %[[EXT]], <i32 16, i32 16, i32 16, i32 16>
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32 float32x4_t test_vcvtq_low_f32_bf16(bfloat16x8_t a) {
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33 return vcvtq_low_f32_bf16(a);
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34 }
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35
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36 // CHECK-LABEL: test_vcvtq_high_f32_bf16
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37 // CHECK: shufflevector <8 x bfloat> %{{.*}}, <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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38 // CHECK: %[[EXT:.*]] = zext <4 x i16> %{{.*}} to <4 x i32>
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39 // CHECK: shl nuw <4 x i32> %[[EXT]], <i32 16, i32 16, i32 16, i32 16>
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40 float32x4_t test_vcvtq_high_f32_bf16(bfloat16x8_t a) {
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41 return vcvtq_high_f32_bf16(a);
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42 }
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43
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44 // CHECK-LABEL: test_vcvt_bf16_f32
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45 // CHECK-A64: %[[CVT:.*]] = call <8 x bfloat> @llvm.aarch64.neon.bfcvtn(<4 x float> %a)
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46 // CHECK-A64: shufflevector <8 x bfloat> %[[CVT]], <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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47 // CHECK-A32-HARDFP: call <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float> %a)
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48 // CHECK-A32-SOFTFP: call <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16(<4 x float> %a)
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49 bfloat16x4_t test_vcvt_bf16_f32(float32x4_t a) {
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50 return vcvt_bf16_f32(a);
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51 }
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52
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53 // CHECK-LABEL: test_vcvtq_low_bf16_f32
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54 // CHECK-A64: call <8 x bfloat> @llvm.aarch64.neon.bfcvtn(<4 x float> %a)
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55 // CHECK-A32-HARDFP: %[[CVT:.*]] = call <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16
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56 // CHECK-A32-HARDFP: shufflevector <4 x bfloat> zeroinitializer, <4 x bfloat> %[[CVT]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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57 // CHECK-A32-SOFTFP: call <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16
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58 // CHECK-A32-SOFTFP: shufflevector <4 x bfloat> zeroinitializer, <4 x bfloat> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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59 bfloat16x8_t test_vcvtq_low_bf16_f32(float32x4_t a) {
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60 return vcvtq_low_bf16_f32(a);
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61 }
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62
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63 // CHECK-LABEL: test_vcvtq_high_bf16_f32
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64 // CHECK-A64: call <8 x bfloat> @llvm.aarch64.neon.bfcvtn2(<8 x bfloat> %inactive, <4 x float> %a)
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65 // CHECK-A32-HARDFP: %[[CVT:.*]] = call <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float> %a)
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66 // CHECK-A32-HARDFP: %[[INACT:.*]] = shufflevector <8 x bfloat> %inactive, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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67 // CHECK-A32-HARDFP: shufflevector <4 x bfloat> %[[CVT]], <4 x bfloat> %[[INACT]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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68 // CHECK-A32-SOFTFP: call <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16(<4 x float> %a)
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69 // CHECK-A32-SOFTFP: shufflevector <8 x bfloat> %{{.*}}, <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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70 // CHECK-A32-SOFTFP: shufflevector <4 x bfloat> %{{.*}}, <4 x bfloat> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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71 bfloat16x8_t test_vcvtq_high_bf16_f32(bfloat16x8_t inactive, float32x4_t a) {
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72 return vcvtq_high_bf16_f32(inactive, a);
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73 }
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74
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75 // CHECK-LABEL: test_vcvth_bf16_f32
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76 // CHECK-A64: call bfloat @llvm.aarch64.neon.bfcvt(float %a)
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77 // CHECK-A32-HARDFP: call bfloat @llvm.arm.neon.vcvtbfp2bf(float %a)
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78 // CHECK-A32-SOFTFP: call bfloat @llvm.arm.neon.vcvtbfp2bf(float %a)
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79 bfloat16_t test_vcvth_bf16_f32(float32_t a) {
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80 return vcvth_bf16_f32(a);
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81 }
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82
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83 // CHECK-LABEL: test_vcvtah_f32_bf16
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84 // CHECK: shl i32 %{{.*}}, 16
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85 float32_t test_vcvtah_f32_bf16(bfloat16_t a) {
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86 return vcvtah_f32_bf16(a);
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87 }
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88
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