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1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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2 // REQUIRES: powerpc-registered-target
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3 // RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \
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4 // RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck \
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5 // RUN: %s -check-prefix=CHECK-LE
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6 // RUN: %clang_cc1 -O2 -target-feature +altivec -target-feature +power8-vector \
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7 // RUN: -triple powerpc64-aix-unknown -emit-llvm %s -o - | FileCheck \
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8 // RUN: %s -check-prefix=CHECK-AIX
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9 #include <altivec.h>
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10 // CHECK-LE-LABEL: @test_subc(
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11 // CHECK-LE-NEXT: entry:
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12 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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13 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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14 // CHECK-LE-NEXT: [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) #[[ATTR3:[0-9]+]]
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15 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>
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16 // CHECK-LE-NEXT: ret <16 x i8> [[TMP3]]
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17 //
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18 // CHECK-AIX-LABEL: @test_subc(
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19 // CHECK-AIX-NEXT: entry:
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20 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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21 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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22 // CHECK-AIX-NEXT: [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) #[[ATTR3:[0-9]+]]
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23 // CHECK-AIX-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>
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24 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP3]]
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25 //
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26 vector unsigned char test_subc(vector unsigned char a, vector unsigned char b) {
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27 return vec_subc_u128(a, b);
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28 }
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29 // CHECK-LE-LABEL: @test_subec(
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30 // CHECK-LE-NEXT: entry:
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31 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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32 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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33 // CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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34 // CHECK-LE-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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35 // CHECK-LE-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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36 // CHECK-LE-NEXT: ret <16 x i8> [[TMP4]]
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37 //
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38 // CHECK-AIX-LABEL: @test_subec(
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39 // CHECK-AIX-NEXT: entry:
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40 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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41 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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42 // CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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43 // CHECK-AIX-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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44 // CHECK-AIX-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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45 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP4]]
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46 //
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47 vector unsigned char test_subec(vector unsigned char a, vector unsigned char b,
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48 vector unsigned char c) {
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49 return vec_subec_u128(a, b, c);
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50 }
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51 // CHECK-LE-LABEL: @test_sube(
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52 // CHECK-LE-NEXT: entry:
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53 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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54 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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55 // CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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56 // CHECK-LE-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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57 // CHECK-LE-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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58 // CHECK-LE-NEXT: ret <16 x i8> [[TMP4]]
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59 //
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60 // CHECK-AIX-LABEL: @test_sube(
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61 // CHECK-AIX-NEXT: entry:
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62 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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63 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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64 // CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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65 // CHECK-AIX-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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66 // CHECK-AIX-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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67 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP4]]
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68 //
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69 vector unsigned char test_sube(vector unsigned char a, vector unsigned char b,
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70 vector unsigned char c) {
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71 return vec_sube_u128(a, b, c);
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72 }
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73 // CHECK-LE-LABEL: @test_sub(
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74 // CHECK-LE-NEXT: entry:
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75 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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76 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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77 // CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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78 // CHECK-LE-NEXT: [[VADDUQM_I_NEG:%.*]] = add <1 x i128> [[TMP0]], [[TMP1]]
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79 // CHECK-LE-NEXT: [[VSUBUQM_I:%.*]] = sub <1 x i128> [[TMP2]], [[VADDUQM_I_NEG]]
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80 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[VSUBUQM_I]] to <16 x i8>
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81 // CHECK-LE-NEXT: ret <16 x i8> [[TMP3]]
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82 //
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83 // CHECK-AIX-LABEL: @test_sub(
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84 // CHECK-AIX-NEXT: entry:
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85 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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86 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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87 // CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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88 // CHECK-AIX-NEXT: [[VADDUQM_I_NEG:%.*]] = add <1 x i128> [[TMP0]], [[TMP1]]
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89 // CHECK-AIX-NEXT: [[VSUBUQM_I:%.*]] = sub <1 x i128> [[TMP2]], [[VADDUQM_I_NEG]]
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90 // CHECK-AIX-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[VSUBUQM_I]] to <16 x i8>
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91 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP3]]
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92 //
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93 vector unsigned char test_sub(vector unsigned char a, vector unsigned char b,
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94 vector unsigned char c) {
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95 return vec_sub_u128(a, vec_add_u128(b, c));
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96 }
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97 // CHECK-LE-LABEL: @test_addc(
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98 // CHECK-LE-NEXT: entry:
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99 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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100 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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101 // CHECK-LE-NEXT: [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) #[[ATTR3]]
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102 // CHECK-LE-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>
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103 // CHECK-LE-NEXT: ret <16 x i8> [[TMP3]]
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104 //
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105 // CHECK-AIX-LABEL: @test_addc(
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106 // CHECK-AIX-NEXT: entry:
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107 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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108 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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109 // CHECK-AIX-NEXT: [[TMP2:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]]) #[[ATTR3]]
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110 // CHECK-AIX-NEXT: [[TMP3:%.*]] = bitcast <1 x i128> [[TMP2]] to <16 x i8>
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111 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP3]]
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112 //
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113 vector unsigned char test_addc(vector unsigned char a, vector unsigned char b) {
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114 return vec_addc_u128(a, b);
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115 }
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116 // CHECK-LE-LABEL: @test_addec(
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117 // CHECK-LE-NEXT: entry:
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118 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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119 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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120 // CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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121 // CHECK-LE-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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122 // CHECK-LE-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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123 // CHECK-LE-NEXT: ret <16 x i8> [[TMP4]]
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124 //
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125 // CHECK-AIX-LABEL: @test_addec(
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126 // CHECK-AIX-NEXT: entry:
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127 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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128 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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129 // CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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130 // CHECK-AIX-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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131 // CHECK-AIX-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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132 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP4]]
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133 //
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134 vector unsigned char test_addec(vector unsigned char a, vector unsigned char b,
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135 vector unsigned char c) {
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136 return vec_addec_u128(a, b, c);
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137 }
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138 // CHECK-LE-LABEL: @test_adde(
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139 // CHECK-LE-NEXT: entry:
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140 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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141 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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142 // CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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143 // CHECK-LE-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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144 // CHECK-LE-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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145 // CHECK-LE-NEXT: ret <16 x i8> [[TMP4]]
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146 //
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147 // CHECK-AIX-LABEL: @test_adde(
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148 // CHECK-AIX-NEXT: entry:
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149 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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150 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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151 // CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C:%.*]] to <1 x i128>
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152 // CHECK-AIX-NEXT: [[TMP3:%.*]] = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> [[TMP0]], <1 x i128> [[TMP1]], <1 x i128> [[TMP2]]) #[[ATTR3]]
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153 // CHECK-AIX-NEXT: [[TMP4:%.*]] = bitcast <1 x i128> [[TMP3]] to <16 x i8>
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154 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP4]]
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155 //
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156 vector unsigned char test_adde(vector unsigned char a, vector unsigned char b,
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157 vector unsigned char c) {
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158 return vec_adde_u128(a, b, c);
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159 }
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160 // CHECK-LE-LABEL: @test_add(
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161 // CHECK-LE-NEXT: entry:
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162 // CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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163 // CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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164 // CHECK-LE-NEXT: [[VADDUQM_I:%.*]] = add <1 x i128> [[TMP1]], [[TMP0]]
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165 // CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <1 x i128> [[VADDUQM_I]] to <16 x i8>
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166 // CHECK-LE-NEXT: ret <16 x i8> [[TMP2]]
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167 //
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168 // CHECK-AIX-LABEL: @test_add(
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169 // CHECK-AIX-NEXT: entry:
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170 // CHECK-AIX-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[A:%.*]] to <1 x i128>
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171 // CHECK-AIX-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[B:%.*]] to <1 x i128>
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172 // CHECK-AIX-NEXT: [[VADDUQM_I:%.*]] = add <1 x i128> [[TMP1]], [[TMP0]]
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173 // CHECK-AIX-NEXT: [[TMP2:%.*]] = bitcast <1 x i128> [[VADDUQM_I]] to <16 x i8>
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174 // CHECK-AIX-NEXT: ret <16 x i8> [[TMP2]]
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175 //
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176 vector unsigned char test_add(vector unsigned char a, vector unsigned char b) {
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177 return vec_add_u128(a, b);
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178 }
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