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150
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1 // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-feature +neon \
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207
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2 // RUN: -target-feature +sha2 -target-feature +aes \
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3 // RUN: -target-cpu cortex-a57 -emit-llvm -O1 -o - %s | FileCheck %s
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150
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4
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5 // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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207
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6 // RUN: -target-feature +sha2 -target-feature +aes \
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7 // RUN: -emit-llvm -O1 -o - %s | FileCheck %s
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150
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8 // RUN: not %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
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9 // RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
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10
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11 // Test new aarch64 intrinsics and types
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12
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13 #include <arm_neon.h>
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14
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15 uint8x16_t test_vaeseq_u8(uint8x16_t data, uint8x16_t key) {
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16 // CHECK-LABEL: @test_vaeseq_u8
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17 // CHECK-NO-CRYPTO: warning: implicit declaration of function 'vaeseq_u8' is invalid in C99
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18 return vaeseq_u8(data, key);
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19 // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aese(<16 x i8> %data, <16 x i8> %key)
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20 }
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21
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22 uint8x16_t test_vaesdq_u8(uint8x16_t data, uint8x16_t key) {
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23 // CHECK-LABEL: @test_vaesdq_u8
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24 return vaesdq_u8(data, key);
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25 // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesd(<16 x i8> %data, <16 x i8> %key)
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26 }
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27
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28 uint8x16_t test_vaesmcq_u8(uint8x16_t data) {
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29 // CHECK-LABEL: @test_vaesmcq_u8
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30 return vaesmcq_u8(data);
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31 // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesmc(<16 x i8> %data)
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32 }
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33
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34 uint8x16_t test_vaesimcq_u8(uint8x16_t data) {
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35 // CHECK-LABEL: @test_vaesimcq_u8
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36 return vaesimcq_u8(data);
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37 // CHECK: call <16 x i8> @llvm.{{arm.neon|aarch64.crypto}}.aesimc(<16 x i8> %data)
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38 }
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39
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40 uint32_t test_vsha1h_u32(uint32_t hash_e) {
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41 // CHECK-LABEL: @test_vsha1h_u32
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42 return vsha1h_u32(hash_e);
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43 // CHECK: call i32 @llvm.{{arm.neon|aarch64.crypto}}.sha1h(i32 %hash_e)
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44 }
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45
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46 uint32x4_t test_vsha1su1q_u32(uint32x4_t w0_3, uint32x4_t w12_15) {
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47 // CHECK-LABEL: @test_vsha1su1q_u32
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48 return vsha1su1q_u32(w0_3, w12_15);
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49 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su1(<4 x i32> %w0_3, <4 x i32> %w12_15)
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50 }
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51
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52 uint32x4_t test_vsha256su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7) {
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53 // CHECK-LABEL: @test_vsha256su0q_u32
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54 return vsha256su0q_u32(w0_3, w4_7);
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55 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
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56 }
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57
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58 uint32x4_t test_vsha1cq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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59 // CHECK-LABEL: @test_vsha1cq_u32
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60 return vsha1cq_u32(hash_abcd, hash_e, wk);
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61 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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62 }
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63
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64 uint32x4_t test_vsha1pq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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65 // CHECK-LABEL: @test_vsha1pq_u32
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66 return vsha1pq_u32(hash_abcd, hash_e, wk);
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67 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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68 }
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69
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70 uint32x4_t test_vsha1mq_u32(uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk) {
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71 // CHECK-LABEL: @test_vsha1mq_u32
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72 return vsha1mq_u32(hash_abcd, hash_e, wk);
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73 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
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74 }
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75
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76 uint32x4_t test_vsha1su0q_u32(uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11) {
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77 // CHECK-LABEL: @test_vsha1su0q_u32
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78 return vsha1su0q_u32(w0_3, w4_7, w8_11);
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79 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha1su0(<4 x i32> %w0_3, <4 x i32> %w4_7, <4 x i32> %w8_11)
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80 }
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81
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82 uint32x4_t test_vsha256hq_u32(uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk) {
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83 // CHECK-LABEL: @test_vsha256hq_u32
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84 return vsha256hq_u32(hash_abcd, hash_efgh, wk);
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85 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
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86 }
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87
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88 uint32x4_t test_vsha256h2q_u32(uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk) {
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89 // CHECK-LABEL: @test_vsha256h2q_u32
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90 return vsha256h2q_u32(hash_efgh, hash_abcd, wk);
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91 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
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92 }
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93
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94 uint32x4_t test_vsha256su1q_u32(uint32x4_t w0_3, uint32x4_t w8_11, uint32x4_t w12_15) {
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95 // CHECK-LABEL: @test_vsha256su1q_u32
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96 return vsha256su1q_u32(w0_3, w8_11, w12_15);
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97 // CHECK: call <4 x i32> @llvm.{{arm.neon|aarch64.crypto}}.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
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98 }
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