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annotate llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children 1f2b6ac9f198
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207
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
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2 ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx810 -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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3 ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX9 %s
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4
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5 ; A test case that originally failed in divergence calculation
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6 ; Implementation has to identify all formal args that can be a source of divergence
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7
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8 @0 = external dso_local addrspace(4) constant [6 x <2 x float>]
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9
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10 ; GCN-LABEL: {{^}}_amdgpu_vs_main:
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11 ; GCN-NOT: v_readfirstlane
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12 ; PRE-GFX9: flat_load_dword
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13 ; GFX9: global_load
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14 define dllexport amdgpu_vs void @_amdgpu_vs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8) local_unnamed_addr #0 {
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15 .entry:
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16 %tmp = add i32 %arg4, %arg8
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17 %tmp9 = sext i32 %tmp to i64
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18 %tmp10 = getelementptr [6 x <2 x float>], [6 x <2 x float>] addrspace(4)* @0, i64 0, i64 %tmp9
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19 %tmp11 = load <2 x float>, <2 x float> addrspace(4)* %tmp10, align 8
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20 %tmp12 = fadd nnan arcp contract <2 x float> zeroinitializer, %tmp11
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21 %tmp13 = extractelement <2 x float> %tmp12, i32 1
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22 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float undef, float %tmp13, float 0.000000e+00, float 1.000000e+00, i1 true, i1 false) #1
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23 ret void
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24 }
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25
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26 declare i64 @llvm.amdgcn.s.getpc() #0
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27 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
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28
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29 attributes #0 = { nounwind readnone speculatable }
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30 attributes #1 = { nounwind }