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207
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s
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3 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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5
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6 define i32 @s_add_co_select_user() {
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7 ; GFX7-LABEL: s_add_co_select_user:
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8 ; GFX7: ; %bb.0: ; %bb
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9 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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10 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
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11 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0
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12 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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13 ; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6
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14 ; GFX7-NEXT: s_or_b32 s4, s4, s5
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15 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0
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16 ; GFX7-NEXT: s_addc_u32 s4, s6, 0
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17 ; GFX7-NEXT: v_mov_b32_e32 v1, s4
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18 ; GFX7-NEXT: s_cselect_b64 vcc, 1, 0
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19 ; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
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20 ; GFX7-NEXT: v_cmp_gt_u32_e64 vcc, s6, 31
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21 ; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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22 ; GFX7-NEXT: s_setpc_b64 s[30:31]
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23 ;
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24 ; GFX9-LABEL: s_add_co_select_user:
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25 ; GFX9: ; %bb.0: ; %bb
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26 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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27 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
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28 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0
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29 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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30 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6
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31 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
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32 ; GFX9-NEXT: s_addc_u32 s4, s6, 0
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33 ; GFX9-NEXT: s_cselect_b64 vcc, 1, 0
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34 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
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35 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31
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36 ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
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37 ; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
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38 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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39 ; GFX9-NEXT: s_setpc_b64 s[30:31]
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40 ;
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41 ; GFX10-LABEL: s_add_co_select_user:
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42 ; GFX10: ; %bb.0: ; %bb
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43 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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44 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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45 ; GFX10-NEXT: s_mov_b64 s[4:5], 0
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46 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
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47 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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48 ; GFX10-NEXT: v_add_co_u32 v0, s5, s4, s4
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49 ; GFX10-NEXT: s_cmpk_lg_u32 s5, 0x0
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50 ; GFX10-NEXT: s_addc_u32 s5, s4, 0
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51 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0
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52 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31
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53 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, s5, s6
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54 ; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
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55 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
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56 ; GFX10-NEXT: s_setpc_b64 s[30:31]
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57 bb:
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58 %i = load volatile i32, i32 addrspace(4)* null, align 8
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59 %i1 = add i32 %i, %i
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60 %i2 = icmp ult i32 %i1, %i
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61 %i3 = zext i1 %i2 to i32
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62 %i4 = add nuw nsw i32 %i3, 0
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63 %i5 = add i32 %i4, %i
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64 %i6 = icmp ult i32 %i5, %i4
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65 %i7 = select i1 %i6, i32 %i5, i32 0
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66 %i8 = icmp ugt i32 %i, 31
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67 %i9 = select i1 %i8, i32 %i1, i32 %i7
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68 ret i32 %i9
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69 }
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70
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71 define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
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72 ; GFX7-LABEL: s_add_co_br_user:
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73 ; GFX7: ; %bb.0: ; %bb
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74 ; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
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75 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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76 ; GFX7-NEXT: s_add_i32 s1, s0, s0
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77 ; GFX7-NEXT: v_mov_b32_e32 v0, s0
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78 ; GFX7-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0
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79 ; GFX7-NEXT: s_or_b32 s1, vcc_lo, vcc_hi
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80 ; GFX7-NEXT: s_cmp_lg_u32 s1, 0
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81 ; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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82 ; GFX7-NEXT: s_addc_u32 s0, s0, 0
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83 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
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84 ; GFX7-NEXT: s_and_b64 vcc, exec, vcc
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85 ; GFX7-NEXT: s_cbranch_vccnz BB1_2
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86 ; GFX7-NEXT: ; %bb.1: ; %bb0
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87 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
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88 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
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89 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
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90 ; GFX7-NEXT: flat_store_dword v[0:1], v2
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91 ; GFX7-NEXT: s_waitcnt vmcnt(0)
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92 ; GFX7-NEXT: BB1_2: ; %bb1
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93 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
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94 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
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95 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
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96 ; GFX7-NEXT: flat_store_dword v[0:1], v2
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97 ; GFX7-NEXT: s_waitcnt vmcnt(0)
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98 ; GFX7-NEXT: s_endpgm
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99 ;
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100 ; GFX9-LABEL: s_add_co_br_user:
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101 ; GFX9: ; %bb.0: ; %bb
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102 ; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0
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103 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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104 ; GFX9-NEXT: s_add_i32 s1, s0, s0
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105 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
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106 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0
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107 ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
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108 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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109 ; GFX9-NEXT: s_addc_u32 s0, s0, 0
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110 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
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111 ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
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112 ; GFX9-NEXT: s_cbranch_vccnz BB1_2
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113 ; GFX9-NEXT: ; %bb.1: ; %bb0
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114 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
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115 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
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116 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
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117 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
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118 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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119 ; GFX9-NEXT: BB1_2: ; %bb1
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120 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
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121 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
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122 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
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123 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
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124 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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125 ; GFX9-NEXT: s_endpgm
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126 ;
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127 ; GFX10-LABEL: s_add_co_br_user:
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128 ; GFX10: ; %bb.0: ; %bb
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129 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
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130 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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131 ; GFX10-NEXT: s_add_i32 s1, s0, s0
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132 ; GFX10-NEXT: v_cmp_lt_u32_e64 s1, s1, s0
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133 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
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134 ; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0
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135 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
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136 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
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137 ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
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138 ; GFX10-NEXT: s_cbranch_vccnz BB1_2
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139 ; GFX10-NEXT: ; %bb.1: ; %bb0
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140 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
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141 ; GFX10-NEXT: v_mov_b32_e32 v2, 9
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142 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
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143 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
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144 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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145 ; GFX10-NEXT: BB1_2: ; %bb1
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146 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
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147 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
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148 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
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149 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
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150 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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151 ; GFX10-NEXT: s_endpgm
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152 bb:
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153 %i1 = add i32 %i, %i
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154 %i2 = icmp ult i32 %i1, %i
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155 %i3 = zext i1 %i2 to i32
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156 %i4 = add nuw nsw i32 %i3, 0
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157 %i5 = add i32 %i4, %i
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158 %i6 = icmp ult i32 %i5, %i4
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159 %i7 = select i1 %i6, i32 %i5, i32 0
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160 br i1 %i6, label %bb0, label %bb1
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161
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162 bb0:
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163 store volatile i32 9, i32 addrspace(1)* null
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164 br label %bb1
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165
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166 bb1:
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167 store volatile i32 10, i32 addrspace(1)* null
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168 ret void
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169 }
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