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annotate llvm/test/CodeGen/AMDGPU/nor.ll @ 207:2e18cbf3894f

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LLVM12
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Tue, 08 Jun 2021 06:07:14 +0900
parents 1d019706d866
children 1f2b6ac9f198
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207
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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1 ; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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2 ; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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3 ; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
150
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5
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6 ; GCN-LABEL: {{^}}scalar_nor_i32_one_use
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7 ; GCN: s_nor_b32
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8 define amdgpu_kernel void @scalar_nor_i32_one_use(
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9 i32 addrspace(1)* %r0, i32 %a, i32 %b) {
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10 entry:
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11 %or = or i32 %a, %b
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12 %r0.val = xor i32 %or, -1
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13 store i32 %r0.val, i32 addrspace(1)* %r0
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14 ret void
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15 }
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16
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17 ; GCN-LABEL: {{^}}scalar_nor_i32_mul_use
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18 ; GCN-NOT: s_nor_b32
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19 ; GCN: s_or_b32
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20 ; GCN: s_not_b32
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21 ; GCN: s_add_i32
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22 define amdgpu_kernel void @scalar_nor_i32_mul_use(
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23 i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) {
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24 entry:
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25 %or = or i32 %a, %b
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26 %r0.val = xor i32 %or, -1
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27 %r1.val = add i32 %or, %a
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28 store i32 %r0.val, i32 addrspace(1)* %r0
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29 store i32 %r1.val, i32 addrspace(1)* %r1
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30 ret void
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31 }
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32
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33 ; GCN-LABEL: {{^}}scalar_nor_i64_one_use
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34 ; GCN: s_nor_b64
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35 define amdgpu_kernel void @scalar_nor_i64_one_use(
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36 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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37 entry:
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38 %or = or i64 %a, %b
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39 %r0.val = xor i64 %or, -1
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40 store i64 %r0.val, i64 addrspace(1)* %r0
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41 ret void
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42 }
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43
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44 ; GCN-LABEL: {{^}}scalar_nor_i64_mul_use
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45 ; GCN-NOT: s_nor_b64
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46 ; GCN: s_or_b64
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47 ; GCN: s_not_b64
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48 ; GCN: s_add_u32
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49 ; GCN: s_addc_u32
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50 define amdgpu_kernel void @scalar_nor_i64_mul_use(
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51 i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) {
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52 entry:
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53 %or = or i64 %a, %b
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54 %r0.val = xor i64 %or, -1
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55 %r1.val = add i64 %or, %a
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56 store i64 %r0.val, i64 addrspace(1)* %r0
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57 store i64 %r1.val, i64 addrspace(1)* %r1
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58 ret void
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59 }
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60
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61 ; GCN-LABEL: {{^}}vector_nor_i32_one_use
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62 ; GCN-NOT: s_nor_b32
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63 ; GCN: v_or_b32
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64 ; GCN: v_not_b32
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65 define i32 @vector_nor_i32_one_use(i32 %a, i32 %b) {
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66 entry:
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67 %or = or i32 %a, %b
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68 %r = xor i32 %or, -1
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69 ret i32 %r
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70 }
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71
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72 ; GCN-LABEL: {{^}}vector_nor_i64_one_use
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73 ; GCN-NOT: s_nor_b64
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74 ; GCN: v_or_b32
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75 ; GCN: v_or_b32
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76 ; GCN: v_not_b32
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77 ; GCN: v_not_b32
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78 define i64 @vector_nor_i64_one_use(i64 %a, i64 %b) {
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79 entry:
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80 %or = or i64 %a, %b
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81 %r = xor i64 %or, -1
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82 ret i64 %r
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83 }